Computer Organization and Architecture (2-1-1)


SPRING 2020-2021
Lecture: Wednesday (11:00 AM - 1:00 PM); Lab: Monday(5:00 PM - 7:00 PM); Tut: Tuesday(5:00 PM - 7:00 PM);

Lectures/ Tut and Lab evaluation to be held Online via Google Meet

Announcements, Assignment submission and Quiz evaluations via Google Classroom





Course Objective:

This course is primarily meant to teach undergraduate students the basic operations of computing hardware and how it interfaces to software. It would provide the understanding of system-level programming and provide a high-level understanding of the role played by compilers, assemblers, instruction sets, and hardware. Students would know how to represent fixed-point and floating point numbers in computer and develop hardware algorithms using them for fixed-point and floating point arithmetic. The course would display understanding of instruction set of RISC processor and develop understanding of how memory is organised and managed in a modern digital computer, including cache , virtual and physical memory. It discusses input-output units and how they communicate with the processor, and how their performance is computed. Finally the students would be able to analyse the performance of a digital computer using different parameters and profiling results for various algorithms in a benchmark.

Course Outline:

Modules Topics
Module 1 : Introduction - Overview of Computer Organisation and Architecture; Data Representation Introduction to Computer Organization and Architecture; Basic organization of computer and block level description of the functional units; Evolution of Computers, Von Neumann model
Review of Digital Systems - Combinatorial and Sequential logic elements, Memory system design: semiconductor memory technologies, memory organization; Concept of Finite State Machine; Introduction to buses and connecting I/O devices to CPU and Memory, bus structure
Number representation: Binary Data representation, Signed Number representation, Fixed and Floating point data representations. IEEE 754 floating point number representation
Module 2: Instructing a Computer CPU Architecture, Register Organization , Instruction formats, basic instruction cycle, Instruction interpretation and Sequencing, RTL interpretation of instructions, addressing modes, instruction set.
Case study - instruction sets of MIPS processor; Assembly language programming using MIPS instruction set
Module 3: Arithmetic Algorithms Integer Data computation: Addition, Subtraction, Multiplication: Signed multiplication, Booth's algorithm, Division of integers: Restoring and non-restoring division
Floating point arithmetic: Addition, subtraction, multiplication and division
Module 4: Memory Organisation Introduction to Memory and Memory parameters. Classifications of primary and secondary memories. Types of RAM and ROM, Allocation policies, Memory hierarchy and characteristics.
Cache memory: Concept, architecture (L1, L2, L3), mapping techniques. Cache Coherency, Interleaved and Associative Memory Virtual Memory: Concept, Segmentation and Paging , Page replacement policies.
Module 5: I/O Organization and Peripherals Input/output systems, I/O modules and IO processor
Types of data transfer techniques: Programmed I/O, Interrupt driven I/O and DMA.
Module 6 : Assessing and Enhancing Performance of Computer Systems CPU Performance and its Factors, Evaluating Performance
Enhancing Performnace - Pipeline Processing, instruction pipelining, pipeline stages and pipeline hazards,
Parallel Processing Concepts - Flynn's classifications
Specialized Architectures - Multi-core systems, GPU

Text Book:


1.      David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface Morgan Kaufmann ARM Edition, 2010.





1.      John L. Hennessy and David A. Patterson, Computer Architecture -- A Quantitative Approach, 5th Edition, Morgan Kaufmann Publications, Elsevier, Inc., 2012.

2.      Carl Hamachar, Zvonco Vranesic and Safwat Zaky, Computer Organization, McGraw Hill

3.      William Stallings, Computer Organization and Architecture: Designing for Performance, Pearson Education

4.      John P. Hayes , Computer Architecture and Organization, McGraw Hill

5.      Morris Mano , Computer System Architecture, Pearson Education

6.      Michael D. Ciletti , Advanced Digital Design with the Verilog HDL, 2nd Edition, Pearson





Important Instructions:

1.         Classes will be conducted using slide presentation

2.         Official slide sets and miscellaneous study materials from some of the main text books and elsewhere will be uploaded on the web site on a regular basis.

3.         Every student is expected to have access to at least one of the references mentioned above .

4.         Attendance in the classes is mandatory. If the attendance of a student falls below 75% at the end of the C2 component, he/she will be dropped from the course

5.         Grading Policy :

o   30%: Component 1 - Closed book exam (10%); Take home assignment (10%) and Lab assignment (10%)

o   30%: Component 2 - Closed book exam (10%); Take home assignment (10%) and Lab assignment (10%)

o   40%: Component 3 - Closed book written exam

6.         Take home assignments : They will be assigned at the beginning of a module (announcements will be made on the course web-site every week). These assignments will not only help you in development of an in-depth idea of each topic of the course but will also serve to prepare for your written examinations. They will be evaluated during tutorial classes. You will have to explain your solution to the TAs during tutorial classes ( deadlines will be mentioned on the course website) and you may be assigned group projects which have to be demonstrated during tutorial sessions.

7.         All submissions must be made using Google Classroom . You will be notified about mode and way to submit in the tutorial classes. Submissions after the deadline will not be considered.

8.         Academic Integrity Policy: While collaboration on homework is permitted, blatant copying will not be tolerated. Violators, if caught, will subject to penalties ranging from a zero for the homework assignment in question to an being dropped for the course.

Important Links:

WWW Computer Architecture

Tools , Simulators and Benchmarks

Course Content:

Some of the lecture slides and helpful resources provided here have been borrowed from different sources. I would like to thank all the authors of all such resources.

Sl. No.


Reference / Helpful Resources


Homework Assignment



[ Slides ]

[ Video Lecture - Part 1 ]

[ Video Lecture - Part 2 ]


Data Representation

[ Slides ]

[ Video Lecture - Part 1 ]

[ Video Lecture - Part 2 ]

[ Video Lecture - Part 3 ]

Floating Point Data Representation

Data Representation : A quick Reference

Tut1 : Exploring Data Representation




Homework Set 1


Instructing the Computer

[ Slides ]

[ Video Lecture - Part 1 ]

[ Video Lecture - Part 2 ]

Notes on ISA


Case Study - MIPS Instruction Set Architecture

[ Slides ]

[ Video Lecture - Part 1 ]

[ Video Lecture - Part 2 ]

MIPS Instruction Set

[ Slides ]

MIPS Assembly - I

[ Slides ]

MIPS Assembly - II

[ Slides ]

[ Video Lecture - MIPS Assembly I ]

[ Video Lecture - MIPS Assembly II ]

[ Video Lecture - MIPS Assembly III ]

[ Video Lecture - MIPS Assembly IV ]


ARM Instruction Set

MIPS Programming

Tutorial Video on MIPS Programming using MARS - 1

Tutorial Video on MIPS Programming using MARS - 2

Tutorial Video on MIPS Programming using MARS - 3


Digital Systems - Combinational and Sequential Circuits

[ Slides ]

[ Video Lecture - Designing Digital Systems ]

[ Video Lecture - Combinational Circuits Part 1 ]

[ Video Lecture - Combinational Circuits Part 2 ]

Finite State Machine

[ Slides ]

[ Video Lecture - Sequential Circuits Part 1 ]

[ Video Lecture - Sequential Circuits Part 2 ]

Combinational Circuits

Sequential Circuits

Tutorial : Verilog HDL


Modelling FSM in Verilog

HomeWork Set 2


Arithmetic and Logic Unit

[ Slides - ALU I ]

[ Slides - ALU II ]

[ Slides - ALU III ]

[ Video Lecture - ALU I ]

[ Video Lecture - ALU II ]

[ Video Lecture - ALU III ]

[ Video Lecture - ALU IV ]

Arithmetic Circuits

Computer Arithmetic

HomeWork Set 3


CPU Design : Designing the Data Path and Control

[ Slides - CPU Design ]

[ Slides - DataPath Design I ]

[ Slides - DataPath Design II ]

[ Slides - Design of Control Unit ]

[ Video Lecture - CPU Design ]

[ Video Lecture - Design of DataPath ]


Performance of Computer Systems

[ Slides - Measuring Performance ]

[ Video Lecture - Measuring Performance ]


Memory Systems

[ Slides - Memory Systems ]

Cache Memory

[ Slides - Cache Memory ]

[ Video Lecture - Memory Systems ]

[ Video Lecture - Cache Memory I]

[ Video Lecture - Cache Memory II ]


Input Output Organization

[ Slides I - I/O Organization ]

[ Slides II - I/O Organization ]

[ Video Lecture - Input/Output Organization ]



[ Slides - Pipeline ]