Computer Organization and Architecture Lab


SPRING 2018-19
Section B (Friday 3:00-5:00 PM)

Venue: Room-5042, CC3 Building





Course Objective:

The goal of this course is to have students understand and appreciate the principles of computing hardware and how it interfaces to software. It would provide the students the understanding of system-level programming and provide a high-level understanding of the role played by compilers, assemblers, instruction sets, and hardware

Lab Course Outline:


The lab classes will mainly consist of (a) Simulation of Verilog models for digital systems (including data path and control path design of a simple hypothetical CPU) using proprietory/open source simulation tools (b) simulation of ARM/MIPS32 programs using emuARM/SPIM simulator. It is expected that students perform the lab assignments seriously to have a more refined knowledge of the topics.







1.      David A. Patterson and John L. Hennessy,, Computer Organization and Design: The Hardware/Software Interface Morgan Kaufmann ARM Edition, 2010.

2.      Carl Hamachar, Zvonco Vranesic and Safwat Zaky, Computer Organization, McGraw Hill

3.      Donald E. Thomas and Philip R. Moorby, The VerilogĀ® Hardware Description Language, Springer

4.      Michael D. Ciletti , Advanced Digital Design with the Verilog HDL, 2nd Edition, Pearson

5.      Morris Mano , Computer System Architecture, Pearson Education



Important Instructions:

1.         The laboratory assignments will be mainly implementation-oriented which have to be coded in Verilog and ARM/MIPS assembly. The lab assignments will be based on the topics discussed in theoretical lectures.

2.         Every student is expected to have access to at least One of the reference books Gagne.

3.         Attendance in lab classes is mandatory. If the attendance of a student falls below 75%, he/she may expect a "F Grade"

4.         The laboratory course will consist of class assignments as well as take home assignments. .

5.         All class assignemnts have to be done very seriously and should be submitted to the TAs at the end of the class hour. Performance during class assignemnts not only carries wieghtage for grades, they also help in clearing the concepts discussed in theoretical lectures. If a student does not submit the clas assignments or in non-responsive during viva, his/her may expect a "F" grade. Take home assignments help in preparing for the lab exam. .

6.         Tutorial sessions will be conducted by TAs for the first hour of every lab session. Interact with them to clear your doubts regarding the lab assignments..

7.         Grading Policy (For each of Components 1 and 2) :

o   5%: Implementation of the assignment

o   5%: VIVA (each day)




Lab Assignments:

A Nice tutorial on "Programming in Verilog" can be found here


Sl. No.



Helpful Resources


Working with Linux

1. Setting up your environment for programming in Iverilog (Windows/Linux)

2. Tutorial: Verilog Programming using Iverilog Simulator



Assignment 1

Assignment 2

1. Handout : Verilog HDL


FSM Design in Verilog


MIPS Assembly Language Programming Using MARS 1

MIPS Assembly Language Programming Using MARS 2

Getting Started with MIPS using MARS

Tut 1 : MIPS Programming Using MARS

MIPS Assignment 1

MIPS Assignment 2


MIPS Architecture

MIPS Instruction Set

MIPS Programming

MARS Simulator


Tut2 : Using the cache simulator

MIPS Assignment 3