Dr.Bibhas Ghoshal
Assistant Professor
Department of Information & Technology
Indian Institute of Information Technology
Allahabad 211 012, India
Office
Room No 5158, CC3 building
Phone: +91-0532-2922419
Residence
Quarter: H-14 (H Block)
Phone: +91-0532-2922690
Email
bibhas.ghoshal@iiita.ac.in
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Home | Publications | Teaching | Projects | Research | Students | Background | Miscellaneous
Welcome :-)
I am presently working as Assistant Professor in the Department of Information Technology at the Indian Institute of Information Technology Allahabad. My research interests lie broadly in the field of Computer Systems. Specifically, I work in problems related to Embedded and High Performance Computing systems, Internet of Things, Power Aware Compilers, System Software, Computer Architecture (focussed on Data Mining and Machine learning algorithms), Design and Test of VLSI systems (focussed on Network-on-chip architectures).
News
- New Conference Paper Published : " Improved Community Interaction Through Context Based Citation Analysis; Saha B., Anand T., Sharma A., Ghoshal B.,In: Mining Intelligence and Knowledge Exploration. MIKE 2017; Lecture Notes in Computer Science, vol 10682. Springer, Cham,"
[Download]
- New Journal Paper Published : Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs ; B Ghoshal, C Mandal, I Sengupta; Integration, the VLSI Journal, Elsevier, 2017 [Download]
- Dr. Bibhas Ghoshal's proposal is one of the 259 proposals selected from 2612 project proposals received under IMPRINT Call for Proposals. The ~10% of submitted proposals were selected after the 2612 proposals were reviewed by more than 500 reviewers, in three stages, over the last six months. His submitted proposal number 7482F title Power Aware Compiler for Embedded Processors has been approved for financial support by the Apex Committee of IMPRINT in its meeting held on 28 September 2016. Please refer to the Project heading on my website for details. The list of proposals accepted under the prestigious IMPRINT scheme can ve viewed at IMPRINT Final Approved Proposals
Information for Students
1. Aspiring PhD students willing to work with me in any of the above mentioned research fields may apply for the PhD program at IIIT Allahabad [Application link]
2. If you are a graduate student (preferably with CS/IT/ECE background) and wish to work as summer intern under my supervision, send an email to srip@iiita.ac.in with your latest resume as attachment supported by a statement of purpose
Journal Papers
- Bibhas Ghoshal; Kanchan Manna; Sanatanu Chattopadhyay; Indranil Sengupta, "In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.01, pp.393-397;
doi: 10.1109/TVLSI.2015.2393714
[Download]
- Bibhas Ghoshal; C Mandal; Indranil Sengupta, "Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs," Integration, The VLSI Journal, Elsevier, 2017; doi:https://doi.org/10.1016/j.vlsi.2017.06.011
[Download]
Conference Papers
- Saha B., Anand T., Sharma A., Ghoshal B., "Improved Community Interaction Through Context Based Citation Analysis. In: Ghosh A., Pal R., Prasath R. (eds) Mining Intelligence and Knowledge Exploration. MIKE 2017. Lecture Notes in Computer Science, vol 10682. Springer, Cham,"
[Download]
- Bibhas Ghoshal; Chittaranjan Mandal; Indranil Sengupta, "Re-using Refresh for Self-Testing DRAMs," Proceedings of the International Symposium on Electronic System Design (ISED), NTU Singapore, pp. 118-122, 10-12 December 2013,
doi: 10.1109/ISED.2013.30
[Download]
- Bibhas Ghoshal; Indranil Sengupta, "A Distributed BIST Scheme for NoC-Based Memory Cores," Proceedings of the Euromicro Conference on Digital System Design (DSD), Santander, Spain, pp. 567-574, 4-6 September 2013,
doi: 10.1109/DSD.2013.67
[Download]
- Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay,
"Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip", Proceedings of the 16th International Symposium on Progress in VLSI Design and Test (VDAT), Shibpur, India, pp. 343-349, 1-4 July, 2012,
[Download]
Thesis
- PhD Thesis: Improved Test Techniques For
Network-on-Chip Based Memory Systems, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Jan 2015.
[Download]
| Current Semester
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| Core : Operating System |
| [Theory]
[Lab]
| | Introduction to Programming |
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| Other Courses Taught
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| Computer Organization and Architecture [2015,2016,2017,2018] |
| [Theory]
[Lab]
| | Distributed Systems[2016,2017,2018] |
| [Course website]
| | Elective : Embedded System : Modelling, Design and Analysis[2016,2017,2018] |
| [Course website]
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Research interests
Embedded and Real time System
VLSI Design and Test
Internet of Things
System software
Computer Architecture (focussed on Data Mining and Machine learning applications)
CAD for VLSI
Distributed Systems
Computer System Lab @ IIIT Allahabad
At IIIT Allahabad, we have started the Computer System Laboratory with the aim to develop an independent research wing specialising in areas of high performance computing, parallel/distributed systems, energy efficient systems, security aware systems. In addition the lab supports studies in other branches of computational science and electrical engineering such as artificial intelligence, machine learning, supercomputing, VLSI, CAD, and computer architecture. The research focus of the Computer Systems Lab is both experimental and theoretical, encompassing major domains of computer science such as special computer architectures, operating system, real time systems, programming languages, compilers, computer networking,
reliability and fault tolerance, integrated circuit design and hardware security.
Graduated (M.Tech)
- Jaswinder Singh Sodhi, 2017.
- Balasaheb Dhabade, 2016.
- Bancha Dutta, 2016.
- Reetesh Agarwal, 2016.
- Ritika Khurana, 2015.
(Co-supervisor - Dr. Satish Singh)
- Tanu Ginotra, 2015.
(Co-supervisor - Dr. Satish Singh)
Pursuing
- Ankur Gogoi, Integrated M.Tech-Ph.D.
Tentative Title : A Learning Based Compiler Optimization for Embedded and High Performance Applications
- Akash Sachan, Ph.D.
Tentative Title : Power Aware Compilation in LLVM framework
- Rakesh Kumar,Ph.D.
Tentative Title : Thermal Aware Compiler Framework for Embedded Applications
Sponsored Projects
- Project Title : Power Aware Compiler for Embedded Processors
Sponsor: Ministry of Human Resource and Development, Govt. of India,IMPRINT
India Program
Role : Principal Investigator
Co-Principal Investigator : Professor Indranil Sengupta , Professor, Dept. of CSE, IIT KGP
Department : Department of Information Technology, IIIT Allahabad
Total Budget : 40.42 Lakhs
Tenure : 2 years
- Project Title : Smart Street Lighting System
Sponsor: DIC SPOKE at IIIT Allahabad
Role : Co-PI
Department : Department of Information Technology, IIIT Allahabad
Publications
Publications of Dr. Bibhas Ghoshal
Journal Papers
- Bibhas Ghoshal; Kanchan Manna; Sanatanu Chattopadhyay; Indranil Sengupta, "In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.PP, no.99, pp.1,1,
doi: 10.1109/TVLSI.2015.2393714
[Download]
Conference Papers
- Saha B., Anand T., Sharma A., Ghoshal B., "Improved Community Interaction Through Context Based Citation Analysis. In: Ghosh A., Pal R., Prasath R. (eds) Mining Intelligence and Knowledge Exploration. MIKE 2017. Lecture Notes in Computer Science, vol 10682. Springer, Cham,"
[Download]
- Bibhas Ghoshal; Chittaranjan Mandal; Indranil Sengupta, "Re-using Refresh for Self-Testing DRAMs," Proceedings of the International Symposium on Electronic System Design (ISED), NTU Singapore, pp. 118-122, 10-12 December 2013,
doi: 10.1109/ISED.2013.30
[Download]
- Bibhas Ghoshal; Indranil Sengupta, "A Distributed BIST Scheme for NoC-Based Memory Cores," Proceedings of the Euromicro Conference on Digital System Design (DSD), Santander, Spain, pp. 567-574, 4-6 September 2013,
doi: 10.1109/DSD.2013.67
[Download]
- Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay,
"Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip", Proceedings of the 16th International Symposium on Progress in VLSI Design and Test (VDAT), Shibpur, India, pp. 343-349, 1-4 July, 2012,
[Download]
Thesis
- PhD Thesis: Improved Test Techniques For
Network-on-Chip Based Memory Systems, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Jan 2015.
[Download]
Miscellaneous information
Web-pages:
iiita |
IITKGP |
Social networking sites:
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Linkedin |
Research Gate |
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