Dr. Manish Goswami holds the position of an Associate Professor at Indian Institute of Information Technology (IIIT-A). He joined IIIT-A in the year 2008 in the Electronics and Communication Engg Deptt. He has taught several courses at the Bachelors and the Master levels at IIIT-A. As an academician he puts in 18+ fruitful years in the field of teaching and research. Prior to his expertise here at IIIT-A he served as a faculty in many other universities. He is the senior member of IEEE and VLSI Society of India.
To add to his merits, he currently holds the position of Associate Dean (Admission, Assessment and Award- AAA) at the Indian Institute of Information Technology, Allahabad.Prior to that he worked as HoD and Chief Proctor at IIIT-A from July 2017 to June 2019.
Besides research and academics, his present work also involves setting up and establishing a collaboration for the chip fabrication work at IIIT-A.
Dr. Goswami and his team has designed, fabricated and successfully tested variable resolution ADC chip.
His research interest includes Analog and Mixed Signal VLSI design Circuits, Low Power VLSI Circuit Design, Data Converters, Digital Design etc.
He’s also guiding students for Ph.D and M.Tech thesis.
Apart from academics Dr. Goswami loves playing badminton, chess, carom and has been actively participating in the overall developmental activities of the institute.

Work Experience

Working in Indian Institute of Information Technology Allahabad (IIIT-A) – a Govt. of India organization established as Center of Excellence in Information Technology and Allied Areas since June 2008-till date

  • Started my career in IIITA as Lecturer and then promoted to Assistant Professor and later Associate Professor Electronics and Communication Deptt.
    • Work includes research and teaching M.Tech and B.Tech students
    • Establishment of Laboratories
    • Training the students and guiding MTech Thesis & Ph.D scholars
    • Contribution in M.Tech and B.Tech Curricula
    • Establishing Chip-fabrication (Foundry Support) facility and handling of microelectronics softwares
    • Microelectronics Stream coordinator
    • Contributing in other extra-curricular activities of the institute etc.
  • July 2005- May 2008
    Worked as Lecturer in Birla Institute of Technology (B.I.T) Mesra, Ranchi.
    • Work includes research and teaching M.Tech and B.Tech students
    • Established Laboratories and Guided MTech and BTech Thesis
    • Developed courses for M.Tech and B.Tech streams
    • Handled Registration activities, Website extra-curricular activities etc.
  • July 2002-June 2005
    Worked as Lecturer and Incharge–ECE deptt. in Jaipur Engineering College and Research Centre (J.E.C.R.C) Jaipur.
    • Handling the departmental activities, Teaching B.Tech students, Exam Incharge, Team member of planning and Improvement Cell etc.

Administrative Experience

  • Worked as HoD, Electronics and Communication Deptt IIITA
  • Worked as Chief Proctor, IIITA
  • Worked as Coordinator, Electronics and Communication Deptt IIITA
  • Worked as Incharge Exam & Admission Cell in I.I.I.T-A
  • Worked as Warden Boys Hostel,I.I.I.T-A.
  • Worked as Incharge, Electronics and Communication Deptt, JECRC Jaipur

Academic Achievements

  • 5 Ph.D awarded under my supervision
  • 3 Ph.D currently enrolled under my supervision
  • Guided more than 50 Mtech thesis and few currently undergoing.

Research Interest

  • Analog and Mixed Signal VLSI design Circuits
  • Low Power Circuit Design
  • Data Converters
  • Memory Design


  • Doctor of Philosophy (Ph.D), Submitted 2010 Awarded 2012 Specialization: VLSI Design
    B.I.T Mesra, Ranchi, India
    Topic: Offset and noise cancellation suitable for biomedical and other low frequency signal recording.
  • Masters of Engineering (M.E), 2002
    M.N.I.T Jaipur, Rajasthan with First Class.
  • Bachelors of Engineering (B.E), 1998
    Mumbai University with First Class.

Technical Skills

  • Hardware description Language, Verilog
  • Programming Language C, C++, MATLAB
  • Simulation and Layout Tool Cadence, Tanner, Model Sim, MATLAB, Xilinx, Active HDL, Synplify Pro, etc.


ASIC Implementation of low power variable resolution ADC

High resolution ADC dissipates high power and occupies large silicon area. A solution to save power in ADC is therefore to detect the current operating condition and vary the resolution accordingly.

In this ADC design, resolution is dynamically adjusted according to the given channel conditions. The approach followed in saving power is done by switching some of the stages of the ADC to the standby mode (depending upon the input strength) where power dissipation is only due to the leakage current.

The variable resolution ADC has been designed using Tanner tool on 500nm CMOS technology (AMIS_0.5_CFN kit) and chip is fabricated from MOSIS foundry.

This is the first chip fabrication done by my group in IIITA .

An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC

Comparators are considered to be one of the rudimentary building blocks in most ADCs. Major criterion for an ADC design is high speed, low power and lesser real estate over the chip. In the conventional dynamic latched comparators a small input-voltage difference at the input terminals is pulled up to a full scale digital level in a short span of time, by a positive feedback mechanism (regenerative latch). Due to the random offset errors and internal parasitic/external load capacitances mismatches they suffer a lot of accuracy issues. To overcome this inaccuracy issue, the conventional architecture used a separate preamplifier stage anteceding the positive feedback stage due to which it could amplify a small difference in the input voltage to a full scale digital output, negating the kickback noise. But for an ADC with a feature of high speed and low power application, a comparator without the preamplifier is preferred since it suffers from high static power dissipation. The present work deals with increasing the speed of conversion for an 8-bit ASAR ADC which is done by incubating a modified dynamic latch based comparator as proposed. In the reset phase the output nodes has to be charged up to the initial supply voltage level. This charging of the output nodes induces latency in the process of comparison. We propose a modified approach to tackle this dead time required to reset and improve the speed of comparison. This will in turn make the ASAR ADC to fasten the process of conversion.


Special Manpower Development Programme Chip to System design

Low Power High Speed True Random Number Generator for Cryptographic and Security Application

Random number generators (RNG) are pivotal ingredients in the implementation of many security schemes and are regarded as an essential component in modern cryptography. RNG generates random numbers (RNs) which are used in applications to generate confidential keys, padding and authenticating protocols, vector generation, lottery games, IT security products, smart card, and even in countermeasures against the attack. RNs are used to provide the encryption of information by considering private keys and cypher to maintain the security. In the current era, it is noticeable that random bit streams are in high demand and are extensively used in different applications such as digital signature algorithms, system testing, cryptography, Monte Carlo methods in statistics etc. Now a day, many processors are provided with cryptographic coprocessors that allow the entry to hardware generated random streams as in the software functions. However, each application requires RNs to be true in nature. RNG are classified as pseudo RNG (PRNG) and true RNG (TRNG). PRNG is a device that generates a sequence of numbers that appears to be random but are completely deterministic. The PRNG requires some seeds which are converted to RNs with the help of an algorithmic function. A TRNG on the other hand generates RNs with the help of some physical phenomenon such as jitter, meta-stability, quantum noise, chaos etc. The RNs from TRNG are unpredictable numbers that have no defined pattern.

Awards & Honours

  1. A team under my supervision had secured the 2ndin All India Synopsys Design Contest 2017.
  2. The team under my supervision has won 1st place in All India Mentor Graphics University Design contest 2016.
  3. Awarded financial support from SERB (DST) under International Travel Grant scheme for presenting research paper at Montpellier, France.
  4. The team under my supervision has won All India Mentor Graphics University Design contest 2014 –prize won 1.5 L
  5. PI of SMDPC2SD project of Govt of India
  6. Co-PI in DST awarded sponsored project on Solar Cell The team under my supervision Runners Up in Cadence All India Design contest 2013–prize won .5 L
  7. Top 5 Finalist in Cadence All India Design contest 2012
  8. Went to EPFL Switzerland for 1 month under the Indo Swiss Joint Research Programme (ISJRP) in the project "Micro and Nanoelectronic Devices and Technologies for Environment Monitoring".
  9. Presented a expert talk on –VLSI design during the national workshop on “Electronics System Design and Manufacturing” held on July 18, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi
  10. Presented a expert lecture during the workshop on- Advanced VLSI Design Automation at Sam Higginbottom Institute of Agriculture, Technolgy & Sciences (Allahabad Agriculture University) - held on 8th Sept 2012.
  11. Presented a expert talk on –Crosstalk and noise in digital Systems during the national workshop on “Timing Analysis of Digital VLSI Circuits” held on Nov 3-4, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi.
  12. Best Research Paper Award in IEEE Int. Conf. on Emerging Trends in Elect. Comp. Tech., India.
  13. Throughout topper at B.E level and GATE Qualified.
  14. Established collaboration for the chip fabrication work in IIIT-A.


  1. Sajai Vir Singh, Manish Goswami and Ravindra Singh Tomar, "A Current Tunable Mixed Mode ZC-CCTAs based Resistor less Universal Filter", Journal of Circuits, Systems and Computers, 2021.
  2. Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami and Prasanna Kumar Misra, "A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit", Analog Integrated Circuits and Signal Processing, 2021.
  3. Jitendra Kumar Mishra; Prasanna Kumar Misra and Manish Goswami, "A Low Power 7T SRAM cell using Supply Feedback Technique at 28nm CMOS Technology", 7th International Conference on Signal Processing and Integrated Networks (SPIN), 2020.
  4. Rajesh Kumar Jha, Prashant Singh, Upendra Kashniyal, Manish Goswami and B. R. Singh, "Impact of  HfO2 buffer layer on the electrical characteristics of ferroelectric/high‑k gate stack for nonvolatile memory applications", Applied Physics A, 2020.
  5. Rajesh Kumar Jha, Prashant Singh, Manish Goswami and B. R. Singh, "Impact of HfO2 as a Passivation Layer in the Solar Cell Efficiency Enhancement in Passivated Emitter Rear Cell Type", Journal of Nanoscience and Nanotechnology, 2020.
  6. Aryamick Singh, Manish Goswami and Kavindra Kandpal, "Design of a voltage-programmed VTH compensating pixel circuit for AMOLED displays using diode-connected a-IGZO TFT", IET Circuits, Devices & Systems, 2020.
  7. Dhirendra Kumar, Lakshmi Likhitha Mankali, Prasanna Kumar Misra and Manish Goswami, "A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator", IETE Journal of Research, 2020.
  8. Jitendra Kumar Mishra, Prasanna Kumar Misra and Manish Goswami, "Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications", IEEE Asia Pacific Conference on Circuits and Systems, 2020.
  9. Jitendra Kumar Mishra, Bharat Bhushan Upadhyay, Prasanna Kumar Misra and Manish Goswami, "Design and Analysis of SRAM cell using Body Bias Controller for Low Power Applications", Circuits, Systems, and Signal Processing, 2020.
  10. Dipti, Sajai Vir Singh, Rohit Joshi, Prasanna Kumar Misra and Manish Goswami, "A reusable stage based reduced comparator count binary search ADC", Analog Integrated Circuits and Signal Processing, 2020.
  11. Dhirendra Kumar, Rahul Anand, Sajai Vir Singh, Prasanna Kumar Misra, Ashok Srivastava and Manish Goswami, "0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology", IET Circuits, Devices & Systems, 2020.
  12. Jai Shankar Kumar, Babli Kumari, Prashant Kumar, Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami and Prasanna Kumar Misra, "Design of Transceiver at 865–867 MHz Band using UMC 180 nm CMOS Technology", International Symposium on VLSI Design and Test, 2020.
  13. Dhirendra Kumar, Chaitanya Dnyaneshwar Jadhav, Prasanna Kumar Misra and Manish Goswami, "Opto-Radio Noise based True Random Number Generator", International Symposium on VLSI Design and Test, 2020.
  14. Dhirendra Kumar, Rahul Anand and Manish Goswami, "A 138 Mbps jitter based power efficient true random number generator", International Conference on Electronics, Information, and Communication, 2020.
  15. Jitendra Mishra, Harshit Srivastava, Prasanna Kumar Misra and Manish Goswami, “Analytical modelling and design of 9T SRAM cell with leakage control technique”, Analog Integrated Circuit and Signal Processing, 2019.
  16. Jitendra Mishra, Harshit Srivastava, Prasanna Kumar Misra and Manish Goswami, “A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology”, IEEE iSES Conference, 2018.
  17. Dhirendra Kumar, Kasif Nabi, Prasanna Kumar Misra and Manish Goswami, “Modified Tent Map Based Design for True Random Number Generator”, IEEE iSES Conference, 2018.
  18. Divyesh Sachan, Manish Goswami and Prasanna Kumar Misra, “Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications”, IEEE-ICCE, Las Vegas, 2018.
  19. Sreedhar Vineel Reddy Kaipu, Joyline Dsa, Divyesh Sachan, Manish Goswami, “ Fabrication of Flexible Sensors for Electrodermal Activity Measurement”, IEEE-ICM2017, Beirut, Lebanon.
  20. Anush Bekal, Bharathi Mathyarasa, Manish Goswami, Zhou Zhao and Ashok Srivatsava, “6-bit, Reusable Comparator Stage Based Asynchronous Binary-Search SAR ADC Using Smart Switching Network”, IET Circuits, Devices & Systems, 2017.
  21. Anush Bekal, Saloni Varshney, Kamal Prakash Pandey and Manish Goswami, "Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit", International Journal of Electronics, ol.104, Issue. 9, pp.1227-1246, 2017.
  22. Anush Bekal, Shabi Tabassum and Manish Goswami, "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC", Journal of Circuits, Systems, and Computers, vol. 26, Issue 05, May 2017.
  23. Divyesh Sachan, Harish Peta, Kamaldeep Singh Malik and Manish Goswami, “Low power Multi-threshold 7T SRAM Cell", 59th IEEE Midwest Symp. Circ. Systems (MWSCAS), Oct 16-19, Abu Dhabi, UAE, 2016.
  24. Apoorva Pathak, Divyesh Sachan, Harish Peta and Manish Goswami, “A Modified SRAM BASED Low Power Memory Design”, 29th IEEE VLSI Design Conf. (VLSID), Jan 2-4, Kolkata , India 2016.
  25. Anush, Rohit Joshi, Manish Goswami. B. R. Singh and A Srivastava, “An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC”, IEEE ISVLSI, France 2015.
  26. P. Joshi, Manish Goswami and D Pal, “Design of Quadrature Amplitude Modulation based DC offset cancellation circuit,” Int. J. Electronics Letters, March 2015.
  27. Anush, Manish Goswami. B. R. Singh and D. Pal, “A low power 8-bit Asynchronous SAR ADC design using Charge Scaling DAC ” IEEE ISED, 2014.
  28. Saloni, M. Goswami, B R Singh, Ashok Srivastava “Low Power Variable Resolution ADC ” J. of Low Power Electronics Vol 2, No 10, pp. 236-246, 2014.
  29. Ashwath Rao, Anshuman Dwivedi, Manish Goswami, B. R. Singh, “Effect of nitrogen containing plasma on interface properties of sputtered ZrO2 thin films on silicon”, Elsevier Materials Sciences in Semiconductor Processing, Vol 19, pp 145-149, 2014.
  30. Shabi, Anush, and Manish Goswami., “A Low Power Preamplifier Latch based Comparator Using 180nm CMOS Technology” accepted in IEEE Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) -2013.
  31. Jitendra Jain, Shobhit Singh and Manish Goswami, “Design of Wideband Current Conveyor (CC-II) based Oscillator for Low-Voltage Application using 180nm CMOS Technology,” accepted in CARE-2013.
  32. Saloni, Manish Goswami, B R Singh, “4-6 Variable resolution ADC ” accepted in IEEE- ISED -2013 held in NTU Singapore from 12-14 Dec, 2013.
  33. Atul Kumar, Ashwath Rao, Manish Goswami, B. R. Singh, “Electrical Characterization of MfeOS gate stacks for ferrielectric FETs”, Elsevier Materials Sciences in Semiconductor Processings, Vol 16, pp 1603-1607, 2013.
  34. M. Goswami, D. Verma, Saloni and B R Singh, “Reduced Comparator High Speed Low Power Flash ADC using 90nm CMOS Technology”, Springer’s Analog Integrated circuits and Signal Processing, Vol 74, No 1, pp. 267-278, 2013.
  35. Kavindra Kandpal, Saloni Varshney, and Manish Goswami, “A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs,” Journal of Automation and Control Engineering in Vol. 1 No. 3, 2013.
  36. Manish Goswami et al., “High Performance Hardware Implementation of AES using Minimal Resources” accepted in IEEE- ISSP 2013.
  37. Saloni, Manish Goswami, B R Singh, “Comparator-Multiplexer Based 6 bit 1.4GS/s Low Power ADC” accepted in IEEE- DTIS (Design and Technology of Integrated Systems in Nanoscale Era )-2013 held in UAE from 26-28 March 134-139, 2013.
  38. Saloni, Manish Goswami, B R Singh, “A 5-bit 1.5 GS/s ADC Using Reduced Comparator Architecture” accepted in IEEE- IDT (International Design and Test Symposium)-2012 held in Doha.
  39. Hari Kakara, Manish Goswami, and B.R.Singh “Design and Simulation of low-g single axis SOI MEMS Capacitive Accelerometer”, Int. J. Contemporary Research in Engg. Tech, Vol. 2, No 1, pp. 63-69, 2012.
  40. R. Kumari, Manish Goswami, B.R.Singh “The Impact of Channel Engineering on Short Channel Behavior of Nano Fin-FETs”, Int. J. Nanoscience, No 2, pp. 21-26, March, 2012.
  41. Manish Goswami, Manoj Malik, and D Pal, “A Single Channel QAM Based DC Offset Cancellation Circuit for High Gain Instrumentation Amplifier System,” in Proc. Int. Conf. Information, Communication Embedded Systems., vol. 1, Chennai, India, 2012.
  42. Manish Goswami, Prateesh Shukla, Piyush Joshi, Manoj Malik, and D Pal, “A Low Input Referred Noise Amplifier System for Biomedical Application,” in Proc. IEEE Int. Conf. Electronics Computer Technology., vol. 1, Kanyakumari, India, 2012, pp. 430-434. ACCEPTED FOR PUBLICATION IN Journal of Industrial and Intelligent Information.
  43. Akanksha Bansal, Manish Goswami, and B R Singh, “Optimization of Short Channel Effects in sub 40nm Bulk MOSFET Using Halo Doping,” in Proc. IEEE Stu. Conf. Engineering Systems., vol. 1, Allahabad, India, 2012.
  44. Manish Goswami, and Smriti Khanna, “DC Suppressed High Gain Active CMOS Instrumentation Amplifier for Biomedical Application,” in Proc. IEEE Int. Conf. Emerging Trends Elect. Comp. Tech., vol. 1, Nagercoil, India, 2011, pp. 747-751.
  45. Manish Goswami, and Sudhanshu kannoujiya, “High Performance FPGA Implementation of AES Algorithm with 128-Bit Keys,” in Proc. IEEE Int. Conf. Advances Computing Comm., vol. 1, Himarpur, India, 2011, pp. 281-286.
  46. M. Goswami, A. Saha, M. Chandra and D. Pal, “Novel high Speed MCML 8 bit by 8 bit Multiplier,” in Proc. IEEE Int. Conf. Devices and Communication in Eng. Tech., vol. 1, Ranchi, India, 2011, pp. 978-982.
  47. D. Pal, and M. Goswami, “A Clocked High Pass Filter Based Offset Cancellation Technique for High Gain Biomedical Amplifiers,” Int. J. Electronics-Taylor Francis., vol. 97, no. 5, pp. 539- 552, May 2010.
  48. D. Pal, A. Srinivasulu, and M. Goswami, “Novel Current Mode Waveform Generator with independent frequency and Amplitude Control,” in Proc. IEEE Int. Symp. Circuits Systems (ISCAS)., Taipei, Taiwan, 2009, pp. 2946-2949.
  49. R. Sebastian, M. Malik, M. Goswami, and D. Pal, “VLSI Implementation of Controller Architecture Unit of Digital Thermometer Recording System,” in Proc. National Seminar on Devices, Circuits and Comm., vol. 1, Ranchi, India, 2008.
  50. D. Pal, M. Goswami, and G Krishan, “Novel Approach of High Speed Multipliers,” in Proc. IEEE Int. Conf. Recent App. Soft Computing in Eng. Tech., vol. 1, Alwar, India, 2007, pp. 349-352.
  51. G. Krishan, M. Goswami, and N. Khurana, “Design of High Speed Multiplier,” in Proc. National Conference on High Performance Computing for Next Generation., vol. 1, Tangori, Punjab, India, 2007.

Ph.D. Students

  • Saloni Varshney

    email: varshney.shaloni@gmail.com
    Ph.D. Thesis (Awarded): ASIC Implementation of low power, variable resolution ADC.
    Research Interest:VLSI Design, Low Power ADC converter.

  • Anush Bekal

    email: anush.bekal.in@ieee.org
    Ph.D. Thesis (Awarded): Improved Design of Asynchronous ADC with Reduced Comparator Counts
    Tools and Software Using: Cadence Virtuoso, H-Spice, LT Spice, Mentor Graphics Design Compiler Tanner EDA, VCS,.
    Research Interest: Analog IC Design, Analog VLSI Design, Mixed Signal Design, Digital Design, VLSI Circuits

  • Joyline D'sa

    email: rs155@iiita.ac.in
    Ph.D. Thesis (Awarded):Fabrication and Characterization of Polymer based Drug Delivery Devices for their Application in Controlled Release
    Research Interest: .........

  • Divyesh Sachan

    Ph.D. Thesis (Awarded):Performance study of low-power RF components for 5G wireless receiver frontend
    Tools and Software Using:Cadence Virtuoso, PSpice, Tanner, Xilinx
    Research Interest: Analog and Mixed Signal VLSI Design, RF Design

  • Rajesh Kumar Jha

    email: pmi2015004@iiita.ac.in
    Ph.D. Thesis (Awarded):Investigation of High-k Dielectric as a Buffer Layer for the Application in Non-Volatile Memory
    Research Interest: ...........

  • Jitendra Mishra

    email: rse2016506@iiita.ac.in
    Ph.D. Thesis (Pursuing): Enhanced Performance of SRAM using various circuit technique.
    Tools and Software Using:Cadence Virtuoso, Tanner, Xilinx
    Research Interest: Mixed Signal Design, Memory Design, Low power design.

  • Dhirendra Kumar

    email: pmi2015003@iiita.ac.in
    Ph.D. Thesis (Pursuing): Low Power High Speed True Random Number Generator for Cryptography and Security Applications.
    Tools and Software Using:Cadence Virtuoso, Tanner, Xilinx
    Research Interest: Mixed Signal Design, TRNG, Low power design, Non-linear circuits.

  • Dipti

    email: rse2018509@iiita.ac.in
    Ph.D. Thesis (Pursuing): Design of Binary Search ADC with reduced comparator and switching network.
    Tools and Software Using: Cadence Virtuoso, Tanner
    Research Interest: Mixed Signal Design, low power ADC.


E/8, IIIT Jhalwa

Allahabad (U.P)

India, Pin-211012

Email: manishgoswami@iiita.ac.in