I hold the position of Professor at Indian Institute of Information Technology (IIIT-A) from 2022 onwards. I joined IIIT-A in the year 2008 in the Electronics and Communication Engg Deptt. I had taught several courses at the Bachelors and the Master levels at IIIT-A. As an academician I have 22+ fruitful years in the field of teaching and research. Prior to my expertise here at IIIT-A, I served as a faculty in many other universities. I am the senior member of IEEE, Vice Chair of IEEE CAS UP chapter and VLSI Society of India.
To add to my merits, I presently holds the position of Dean (Academic and Research) at the Indian Institute of Information Technology Allahabad. Prior to that, I was Associate Dean (Admission, Assessment and Award- AAA), HoD and Chief Proctor at IIIT-A.
I and my team has designed, fabricated and successfully tested variable resolution ADC chip, True random number generator chip and Binary search ADCs chip.
My research interest includes Analog and Mixed Signal VLSI design Circuits, Low Power VLSI Circuit Design, Data Converters, Digital Design etc.
I am also guiding students for Ph.D and M.Tech thesis. Working professionals from Industry and other organization are working with me.
Apart from academics I love to play badminton, chess, carom and have been actively participating in the overall developmental activities of the institute.

Work Experience

Working in Indian Institute of Information Technology Allahabad (IIIT-A) – “Institute of National Importance” by the Act of the Parliament, Govt. of India since June 2008-till date

  • Started my career in IIITA as Lecturer and then promoted to Assistant Professor, Associate Professor and later Professor Electronics and Communication Deptt.
    • Senior member-IEEE
    • Member, VLSI Society of India
    • Organized special session in iSES-2020
    • Organising SUMMER TRAINING PROGRAM in VLSI design
    • Work includes research and teaching M.Tech and B.Tech students
    • Establishment of Laboratories
    • Training the students and guiding MTech Thesis & Ph.D scholars
    • Contribution in Phd, M.Tech and B.Tech Curricula
    • Establishing Chip-fabrication (Foundry Support) facility and handling of microelectronics softwares
    • Contributing in other extra-curricular activities of the institute etc.
  • July 2005- May 2008
    Worked as Lecturer in Birla Institute of Technology (B.I.T) Mesra, Ranchi.
    • Work includes research and teaching M.Tech and B.Tech students
    • Established Laboratories and Guided MTech and BTech Thesis
    • Developed courses for M.Tech and B.Tech streams
    • Handled Registration activities, Website extra-curricular activities etc.
  • July 2002-June 2005
    Worked as Lecturer and Incharge–ECE deptt. in Jaipur Engineering College and Research Centre (J.E.C.R.C) Jaipur.
    • Handling the departmental activities, Teaching B.Tech students, Exam Incharge, Team member of planning and Improvement Cell etc.

Administrative Experience

  • Working as Dean- Academics and Research from April 2023 till date
  • Worked as Dean- Academics, IIITA
  • Worked as Dean- Research and Development, IIITA
  • Worked as Associate Dean- Admission, Assessment and Award, IIITA
  • Worked as HoD, Electronics and Communication Deptt IIITA
  • Worked as Chief Proctor, IIITA
  • Worked as Coordinator, Electronics and Communication Deptt IIITA
  • Worked as Incharge Exam & Admission Cell in IIITA
  • Worked as Warden Boys Hostel,IIITA
  • Worked as Incharge, Electronics and Communication Deptt, JECRC Jaipur

Academic Achievements

  • 8 Ph.D awarded under my supervision
  • 6 Ph.D currently enrolled under my supervision
  • Guided 50+ Mtech thesis and few currently undergoing.

Research Interest

  • Analog and Mixed Signal VLSI design Circuits
  • Low Power Circuit Design
  • Data Converters
  • Memory Design


  • Doctor of Philosophy (Ph.D), Submitted 2010 Awarded 2012 Specialization: VLSI Design
    B.I.T Mesra, Ranchi, India
    Topic: Offset and noise cancellation suitable for biomedical and other low frequency signal recording.
  • Masters of Engineering (M.E), 2002
    M.N.I.T Jaipur, Rajasthan with First Class.
  • Bachelors of Engineering (B.E), 1998
    Mumbai University with First Class.

Technical Skills

  • Hardware description Language, Verilog
  • Simulation and Layout Tool Cadence, Tanner, Model Sim, MATLAB, Xilinx, Active HDL, Synplify Pro, etc.


ASIC Implementation of low power variable resolution ADC

High resolution ADC dissipates high power and occupies large silicon area. A solution to save power in ADC is therefore to detect the current operating condition and vary the resolution accordingly.

In this ADC design, resolution is dynamically adjusted according to the given channel conditions. The approach followed in saving power is done by switching some of the stages of the ADC to the standby mode (depending upon the input strength) where power dissipation is only due to the leakage current.

The variable resolution ADC has been designed using Tanner tool on 500nm CMOS technology (AMIS_0.5_CFN kit) and chip is fabricated from MOSIS foundry.

This is the first chip fabrication done by my group in IIITA. This design is extended further to binary search ADC.

A reusable stage based reduced comparator count binary search ADC

This design has been fabricated in SCL180nm CMOS technology.

True random number generator using jitter, metastability and current starved topology

THe chip microphotograph for true random number generator (TRNG) fabricated at SCL on 180nm is shown below. The NIST test suite consisted of statistical tests, were developed to verify and check the randomness. This test also defines the different types of randomness present in generated random sequences. The obtained pass efficiency of the proposed design is very high.

7T SRAM cell Using Supply Feedback Technique

Figure depicts the chip microphotograph of 7T SRAM. This design has been fabricated in MOSIS (AMIS) C5X, 1P-2M CMOS process.


Special Manpower Development Programme Chip to System design

Sponsoring agency: MeitY Role: PI
Period: 2014-2019 Amount: Around 90 Lakh

Chip fabricated on SCL180nm technology.

Low Power High Speed True Random Number Generator for Cryptographic and Security Application

Sponsoring agency: DST Role: PI
Period: 2019-2022 Amount: 67.5 Lakh

Chip fabricated on SCL180nm technology.

Awards & Honours

  1. A team under my supervision had secured the 2ndin All India Synopsys Design Contest 2017.
  2. The team under my supervision has won 1st place in All India Mentor Graphics University Design contest 2016.
  3. Awarded financial support from SERB (DST) under International Travel Grant scheme for presenting research paper at Montpellier, France.
  4. The team under my supervision has won All India Mentor Graphics University Design contest 2014 –prize won 1.5 L
  5. PI of SMDPC2SD project of Govt of India
  6. Co-PI in DST awarded sponsored project on Solar Cell The team under my supervision Runners Up in Cadence All India Design contest 2013–prize won .5 L
  7. Top 5 Finalist in Cadence All India Design contest 2012
  8. Went to EPFL Switzerland for 1 month under the Indo Swiss Joint Research Programme (ISJRP) in the project "Micro and Nanoelectronic Devices and Technologies for Environment Monitoring".
  9. Presented a expert talk on –VLSI design during the national workshop on “Electronics System Design and Manufacturing” held on July 18, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi
  10. Presented a expert lecture during the workshop on- Advanced VLSI Design Automation at Sam Higginbottom Institute of Agriculture, Technolgy & Sciences (Allahabad Agriculture University) - held on 8th Sept 2012.
  11. Presented a expert talk on –Crosstalk and noise in digital Systems during the national workshop on “Timing Analysis of Digital VLSI Circuits” held on Nov 3-4, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi.
  12. Best Research Paper Award in IEEE Int. Conf. on Emerging Trends in Elect. Comp. Tech., India.
  13. Throughout topper at B.E level and GATE Qualified.
  14. Established collaboration for the chip fabrication work in IIIT-A.

Selected publications

  1. Manish Goswami , et al “A highly reliable, stacked-capacitor, voltage-programmed pixel circuit using a-IGZO TFTs for AMOLED Displays”, journal of Circuits, Systems and Computers, 2024.
  2. Manish Goswami , et al “Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors” International Journal of Numerical Modelling: Electronic Networks, Devices , 2024.
  3. Manish Goswami , et al “Design and Analysis of Low-Voltage, MOS-only Bandgap Reference Circuit” IEEE International Symposium on Smart Electronic Systems (iSES) , 2023.
  4. Manish Goswami , et al “Multiplexer & Memory Efficient Bit-Reversal Algorithms” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2023.
  5. Manish Goswami , et al “A 2bit/stage Reusability based methodology for designing 8-bit Binary Search ADC” IEEE Region 10 Symposium (TENSYMP) , 2023.
  6. Manish Goswami , et al “Impact of Interface Trap Distribution on the Performance of LTPS TFT” Silicon 15, 2023.
  7. Manish Goswami , et al “Microfabrication and Characterization of Chemically Actuated Implantable PLGA Reservoir-based Device for Controlled Drug Delivery” IETE Journal of Research, 2023.
  8. Manish Goswami , et al “A 0.7 pJ/bit, 1.5 Gbps energy-efficient image-based true random number generator” IETE Journal of Research, 2023.
  9. Manish Goswami , et al “A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay” IEEE International Symposium on Smart Electronic Systems (iSES), 2022.
  10. Manish Goswami , et al “Design of a Low-Voltage and Reduced Programming cycle AMOLED Pixel Circuit using IGZO TFTs” IEEE International Conference on Emerging Electronics (ICEE), 2022.
  11. Manish Goswami , et al “Effect of deep and tail grain boundary trap states on the performance of poly-ZnO TFT” IEEE International Conference of Electron Devices Society Kolkata , 2022.
  12. Manish Goswami , et al “Impact of Gaussian Grain Boundary Trap States on the Performance of the LTPS TFTs” IEEE International Conference of Electron Devices Society Kolkata , 2022.
  13. Manish Goswami , et al “FPGA Based Resource Efficient Simulation and Emulation Of Grover’s Search Algorithm” IEEE 19th India Council International Conference (INDICON), 2022.
  14. Manish Goswami , et al “Design of Hexagonal Oscillator for True Random Number Generation” IEEE International Conference on Electronics, Circuits and Systems , 2022.
  15. Manish Goswami , et al “A 0.18 pJ/Conversion Step Hybrid Structure based ADC” 2nd Asian Conference on Innovation in Technology (ASIANCON), 2022.
  16. Manish Goswami , et al “Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced With Piezoelectric Tactile Sensor for Tumour Detection” International Symposium on VLSI Design and Test, 2022.
  17. Manish Goswami , et al, "A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications", Wireless Personal Communications, 2022.
  18. Manish Goswami , et al, "A 13.8pJ/conv-step binary search ADC with reusable comparator architecture", AEU - International Journal of Electronics and Communications, 2022.
  19. Manish Goswami , et al, "Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications", World Scientific Publishing Company, 2021.
  20. Manish Goswami , et al, IoT Enabled Cost-Effective Integrated Industrial Automation For FMCG Industry", IEEE 8th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), 2021.
  21. Manish Goswami , et al, "Mechanical strain and bias-stress compensated, 6T-1C pixel circuit for flexible AMOLED displays", Microelectronics Journal, 2021.
  22. Manish Goswami , et al,"A 6.22 pJ/conv-step Split Design and Subtractor Based Binary Search ADC", International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), 2021.
  23. Manish Goswami , et al, "Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach", International Conference on Signal Processing and Integrated Networks (SPIN), 2021.
  24. Manish Goswami , et al, "Smart Switching Network based Asynchronous Binary Search ADC", International Conference on Communication information and Computing Technology (ICCICT), 2021.
  25. Manish Goswami , et al, "Design of True Random Number Generator Using Fingerprint as an Entropy Source and Its Implementation in S-Box", Journal of Circuits, Systems and Computers, 2021.
  26. Manish Goswami , et al “A 0.4 mW, 0.27 pJ/Bit True Random Number Generator Using Jitter, Meta-stability and Current Starved Topology” accepted for publication in IET Circuits, Devices & Systems, 2020.
  27. Manish Goswami , et al, “Opto-Radio Noise based True Random Number Generator”, VDAT, 2020.
  28. Manish Goswami , et al, “A reusable stage based reduced comparator count binary search ADC” accepted for publication in Analog Integrated Circuit and Signal Processing, 2020.
  29. Manish Goswami , et al, “A Low Power 7T SRAM cell using Supply Feedback Technique at 28nm CMOS Technology” SPIN, 2020.
  30. A 138 Mbps Jitter Based Power Efficient True Random Number Generator”, IEEE, ICEIC, France, 2020.
  31. Manish Goswami , et al, “Analytical modeling and design of 9T SRAM cell with leakage control technique”, Analog Integrated Circuit and Signal Processing, 2019.
  32. Manish Goswami , et al. “Modified Tent Map Based Design for True Random Number Generator”, IEEE-iSES, 2019.
  33. Manish Goswami , et al. “A 40nm Low Power High Stable SRAM Cell using Separate Read Port and Sleep Transistor Methodology,”IEEE-iSES, 2019.
  34. Manish Goswami , et al. "Design and fabrication of a magnetically actuated non-invasive reusable drug delivery device." Drug development and Industrial Pharmacy (2018): 1-8.
  35. Manish Goswami et al, “ Fabrication of Flexible Sensors for Electrodermal Activity Measurement”, IEEE-ICM2017, Beirut, Lebanon.
  36. Divyesh Sachan, M. Goswami, P. K. Misra, “A High-Q Floating Active Inductor using 130nm BiCMOS Technology and Its Application in IF Band Pass Filter”, Analog Integrated Circuits and Signal Processing, Springer. 2018.
  37. Divyesh Sachan, H. Kumar, M. Goswami, P. K. Misra, “A 2.4GHz low power low phase-noise enhanced FOM VCO for RF Applications”, Wireless Personal Communications, Springer, 101(1), pp.391-403, 2018.
  38. DivyeshSachan, M. Goswami, P. K. Misra, “A Comparative Study of 5G Wireless Receiver Frontend at 28GHz Frequency using RFCMOS and BiCMOS Technologies”, 5th International Conference on Microelectronics, Circuits and Systems, May 2018.
  39. DivyeshSachan, M. Goswami, P. K. Misra, “Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications”, 36th Int. Conference on Consumer Electronics, Las Vegas, USA, Jan. 2018.
  40. DivyeshSachan, Manish Goswami and Prasanna Kumar Misra, “Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications”, IEEE-ICCE, Las Vegas, 2018.
  41. SreedharVineel Reddy Kaipu, JoylineDsa, DivyeshSachan, Manish Goswami, “ Fabrication of Flexible Sensors for Electrodermal Activity Measurement”, IEEE-ICM2017, Beirut, Lebanon.
  42. AnushBekal, BharathiMathyarasa, Manish Goswami, Zhou Zhao and Ashok Srivatsava, “6-bit, Reusable Comparator Stage Based Asynchronous Binary-Search SAR ADC Using Smart Switching Network”, IET Circuits, Devices & Systems, Vol 12, No 1, pp 124-131, 2017.
  43. Manish Goswami et al, “ Linear Relationship ADC with Complementary switch-based bootstarapped sample and hold circuit” Int Journal of Electronics, pp-1427-1446, 2017
  44. Manish Goswami et al, “A Defected Ground Split Ring Resonator for an Ultra-fast Selective Sensing of Glucose content blood plasma” accepted for publication in Journal of Electromagnetic waves and Application, 2017.
  45. Manish Goswami et al, “ Design of a Low Power Wide Range Phase Locked Loop using 180nm CMOS Technology”, IEEE Int. Conf on Sig. Proc. Comm., 2016.
  46. AnushBekal, ShabiTabassum and Manish Goswami, “Low Power Design of a 1V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC,” Journal of Circuits, Systems, and Computers, vol. 26, no. 5, pp. 1750077(1-25), 2016.
  47. Joyline D’sa, Manisha, Manish Goswami and B.R. Singh, “Simulation of Piezoelectrically Actuated Drug Delivery Device for Biomedical Applications”, COMSOI Conf. 2016, Bangalore, India.
  48. AnushBekal, SaloniVarshney, K. Pandey & Manish Goswami, “Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit,” International Journal of Electronics, pp. 1-20, 2017.
  49. DivyeshSachan, Harish Peta, Kamaldeep Singh Malik and Manish Goswami, “Low power multi threshold 7T SRAM cell”, 59th IEEE Midwest Symp. Circ. Systems (MWSCAS), Oct 16-19, 2016, Abu Dhabi, UAE.
  50. Apoorva Pathak, Harish Peta, DivyeshSachan and Manish Goswami, “A Modified SRAM BASED Low Power Memory Design”, accepted for publication in 29th IEEE VLSI Design Conf., Jan 2-4, 2016, Kolkata, India, VLSID.
  51. AnushBekal, Rohit Joshi, Manish Goswami. B. R. Singh and A Srivastava, “An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC” IEEE ISVLSI, France 2015.
  52. P. Joshi, Manish Goswami and D Pal, “Design of Quadrature Amplitude Modulation based DC offset cancellation circuit,” Int. J. Electronics Letters -Taylor Francis., March 2015.
  53. AnushBekal, Manish Goswami. B. R. Singh and D. Pal, “A low power 8-bit Asynchronous SAR ADC design using Charge Scaling DAC ” IEEE ISED, 2014.
  54. Saloni, M. Goswami, B R Singh, Ashok Srivastava “Low Power Variable Resolution ADC” J. of Low Power Electronics Vol 2, No 10, pp.236-246, 2014.
  55. Ashwath Rao, AnshumanDwivedi, Manish Goswami, B. R. Singh, “Effect of nitrogen containing plasma on interface properties of sputtered ZrO2 thin films on silicon”, Elsevier Materials Sciences in Semiconductor Processing, Vol 19, pp 145-149, 2014.
  56. Shabi, Anush, and Manish Goswami., “A Low Power Preamplifier Latch based Comparator Using 180nm CMOS Technology” accepted in IEEE Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) -2013.
  57. Jitendra Jain, Shobhit Singh and Manish Goswami, “Design of Wideband Current Conveyor (CC-II) based Oscillator for Low-Voltage Application using 180nm CMOS Technology,” accepted in CARE-2013.
  58. Saloni, Manish Goswami, B R Singh, “4-6 Variable resolution ADC ” accepted in IEEE- ISED -2013 held in NTU Singapore from 12-14 Dec, 2013.
  59. Atul Kumar, Ashwath Rao, Manish Goswami, B. R. Singh, “Electrical Characterization of MfeOS gate stacks for ferrielectric FETs”, Elsevier Materials Sciences in Semiconductor Processings, Vol 16, pp 1603-1607, 2013.
  60. M. Goswami, D. Verma, Saloni and B R Singh, “Reduced Comparator High Speed Low Power Flash ADC using 90nm CMOS Technology”, Springer’s Analog Integrated circuits and Signal Processing, Vol 74, No 1, pp. 267-278, 2013.
  61. KavindraKandpal, SaloniVarshney, and Manish Goswami, “A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs,” Journal of Automation and Control Engineering in Vol. 1 No. 3, 2013.
  62. Manish Goswami et al., “High Performance Hardware Implementation of AES using Minimal Resources” accepted in IEEE- ISSP 2013.
  63. Saloni, Manish Goswami, B R Singh, “Comparator-Multiplexer Based 6 bit 1.4GS/s Low Power ADC” accepted in IEEE- DTIS (Design and Technology of Integrated Systems in Nanoscale Era )-2013 held in UAE from 26-28 March 134-139, 2013.
  64. Saloni, Manish Goswami, B R Singh, “A 5-bit 1.5 GS/s ADC Using Reduced Comparator Architecture” accepted in IEEE- IDT (International Design and Test Symposium)-2012 held in Doha.
  65. Hari Kakara, Manish Goswami, and B.R.Singh “Design and Simulation of low-g single axis SOI MEMS Capacitive Accelerometer”, Int. J. Contemporary Research in Engg. Tech, Vol. 2, No 1, pp. 63-69, 2012.
  66. R. Kumari, Manish Goswami, B.R.Singh “The Impact of Channel Engineering on Short Channel Behavior of Nano Fin-FETs”, Int. J. Nanoscience, No 2, pp. 21-26, March, 2012.
  67. Manish Goswami, Manoj Malik, and D Pal, “A Single Channel QAM Based DC Offset Cancellation Circuit for High Gain Instrumentation Amplifier System,” in Proc. Int. Conf. Information, Communication Embedded Systems.,vol. 1, Chennai, India, 2012.
  68. Manish Goswami, Prateesh Shukla, Piyush Joshi, Manoj Malik, and D Pal, “A Low Input Referred Noise Amplifier System for Biomedical Application,” in Proc. IEEE Int. Conf. Electronics Computer Technology., vol. 1, Kanyakumari, India, 2012, pp. 430-434. ACCEPTED FOR PUBLICATION IN Journal of Industrial and Intelligent Information.
  69. Akanksha Bansal, Manish Goswami, and B R Singh, “Optimization of Short Channel Effects in sub 40nm Bulk MOSFET Using Halo Doping,” in Proc. IEEE Stu. Conf. Engineering Systems.,vol. 1, Allahabad, India, 2012.
  70. Manish Goswami, and Smriti Khanna, “DC Suppressed High Gain Active CMOS Instrumentation Amplifier for Biomedical Application,” in Proc. IEEE Int. Conf. Emerging Trends Elect. Comp. Tech., vol. 1, Nagercoil, India, 2011, pp. 747-751.
  71. Manish Goswami, and Sudhanshu kannoujiya, “High Performance FPGA Implementation of AES Algorithm with 128-Bit Keys,” in Proc. IEEE Int. Conf. Advances Computing Comm., vol. 1, Himarpur, India, 2011, pp. 281-286.
  72. M. Goswami, A. Saha, M. Chandra and D. Pal, “Novel high Speed MCML 8 bit by 8 bit Multiplier,” in Proc. IEEE Int. Conf. Devices and Communication in Eng. Tech., vol. 1, Ranchi, India, 2011, pp. 978-982.
  73. D. Pal, and M. Goswami, “A Clocked High Pass Filter Based Offset Cancellation Technique for High Gain Biomedical Amplifiers,” Int. J. Electronics-Taylor Francis., vol. 97, no. 5, pp. 539- 552, May 2010.
  74. D. Pal, A. Srinivasulu, and M. Goswami, “Novel Current Mode Waveform Generator with independent frequency and Amplitude Control,” in Proc. IEEE Int. Symp. Circuits Systems (ISCAS)., Taipei, Taiwan, 2009, pp. 2946-2949.
  75. R. Sebastian, M. Malik, M. Goswami, and D. Pal,“VLSI Implementation of Controller Architecture Unit of Digital Thermometer Recording System,” in Proc.National Seminar on Devices, Circuits and Comm., vol. 1, Ranchi, India, 2008.
  76. D. Pal, M. Goswami, and G Krishan, “Novel Approach of High Speed Multipliers,” in Proc. IEEEInt. Conf. Recent App. Soft Computing in Eng. Tech., vol. 1, Alwar, India, 2007, pp. 349-352.
  77. G. Krishan, M. Goswami, and N. Khurana, “Design of High Speed Multiplier,” in Proc. National Conference on High Performance Computing for Next Generation., vol. 1, Tangori, Punjab, India, 2007.

Ph.D. Students

  • Saloni Varshney

    email: saloni.4j8r@gmail.com
    Ph.D. Thesis (Awarded): ASIC Implementation of low power, variable resolution ADC.
    Passing year: 2015

  • Anush Bekal

    email: anush5137@gmail.com
    Ph.D. Thesis (Awarded): Improved Design of Asynchronous ADC with Reduced Comparator Counts.
    Passing year: 2018

  • Joyline D'sa

    email: rs155@iiita.ac.in
    Ph.D. Thesis (Awarded):Fabrication and Characterization of Polymer based Drug Delivery Devices for their Application in Controlled Release.
    Passing year: 2019

  • Divyesh Sachan

    Ph.D. Thesis (Awarded):Performance study of low-power RF components for 5G wireless receiver frontend.
    Passing year: 2019

  • Rajesh Kumar Jha

    email: pmi2015004@iiita.ac.in
    Ph.D. Thesis (Awarded):Investigation of High-k Dielectric as a Buffer Layer for the Application in Non-Volatile Memory.
    Passing year: 2020

  • Jitendra Mishra

    email: jeetu.er@gmail.com
    Ph.D. Thesis (Awarded): Enhanced Performance of SRAM using various circuit technique.
    Passing year: 2022

  • Dhirendra Kumar

    email: omdhir27@gmail.com
    Ph.D. Thesis (Awarded): Low Power High Speed True Random Number Generator for Cryptography and Security Applications.

  • Dipti

    email: dptchandra@gmail.com
    Ph.D. Thesis (Awarded): Proposed Architectures for Binary Search ADC with Improved Performance

  • Saurabh Jaiswal

    email: rse2020505@iiita.ac.in
    Ph.D. Thesis (Pursuing)

  • Ravi S Siddanath

    email: rwe2022004@iiita.ac.in
    Ph.D. Thesis (Pursuing)
    Working in Broadcom

  • Mohit Gupta

    email: rwe2022003@iiita.ac.in
    Ph.D. Thesis (Pursuing)
    Working in Broadcom

  • Nitish Kumar

    email: pmi2022001@iiita.ac.in
    Ph.D. Thesis (Pursuing): PUF based circuits

    Anurag Pandey

    email: pmi2022002@iiita.ac.in
    Ph.D. Thesis (Pursuing): Data Converters


CC-1, Room No. 2102

IIIT Allahabad (U.P)

India, Pin-211012

Email: manishgoswami@iiita.ac.in