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<p>Associate Professor</p> <p style="text-align:justify">Department of Electronics and Communication Engineering, IIIT Allahabad</p> <p><strong>Office: </strong>Room No.<strong> </strong>2224 (CC-I), IIIT Allahabad</p> <p><strong>Email: </strong>prasanna@iiita.ac.in</p> <p><strong>Contact No:</strong> 0532-2922111</p> <p><strong><u>About Me:</u></strong></p> <p style="text-align:justify">I obtained BTech (2005) and PhD (2014) from National Institute of Science and Technology, Berhampur and IIT Kanpur respectively. Since 2014, I am working as a faculty member in the department of Electronics and Communication Engineering at IIIT Allahabad. My specific area of interests are Analog/RF integrated circuit design, VLSI system design and Memory Design. I am associated with the VLSI Design/EDA laboratory at IIIT Allahabad. This laboratory has industry standard EDA tools (Cadence, Synopsys, Mentor Graphics, Xilinx, TCAD) and state-of-the-art technology design kits for designing integrated circuits and systems. The contributors of research work and publication details are given below.</p> <p><strong><u>PhD Students (Awarded):</u></strong></p> <p>1. Dr. Divyesh Sachan, Low Power RF Circuits</p> <p>2. Dr. Jitendra Kumar Mishra, Memory Design</p> <p>3. Dr. Ankita Verma, CMOS Receiver</p> <p>4. Dr. Pritesh Kumar Yadav, CMOS Receiver</p> <p>5. Dr. Sandeep Tripathi, Memory Design</p> <p>6. Dr. Pratiksha Shukla, Low Power Nonvolatile Circuits and Systems</p> <p><strong><u>PhD Students (Ongoing):</u></strong></p> <p>1. Ms. Priyanka Tiwari (Non Volatile Memory)</p> <p>2. Ms. Apsana Khatoon (CMOS Receiver) </p> <p>3. Mr. Sateesh Kourav (Ultra Wideband Transmitter)</p> <p>4. Ms. Sandhya Kannaujiya (Ultra Wideband Receiver)</p> <p>5. Mr. Ram Krishna Sharma (Ultra Wideband Transmitter)</p> <p><strong><u>Journal Publications:</u></strong></p> <p>[1] S. Tripathi, P. K. Yadav, S. Choudhary, and P. K. Misra, “Power Analysis Attack Resilient Novel 9T & 10T NVSRAM for Emerging Memory,” <em>IEEE Magnetics Letters</em>, 2026.</p> <p>[2] P. K. Yadav and P. K. Misra, “A 28-GHz mmWave Receiver Frontend With an Improved FOM of 15.56-dB for 5G New Radio in 130-nm BiCMOS Technology,” <em>IEEE Access</em>, vol. 14, pp. 21200–21212, 2026.</p> <p>[3] S. Tripathi, S. Choudhary, and P. K. Misra, “An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications,” <em>IEEE Transactions on Circuits and Systems-I: Regular Papers</em>, 2023.</p> <p>[4] S. Tripathi, S. Choudhary, and P. K. Misra, “Highly Reliable, Stable and Store Energy Efficient 8T/9T-2D-2MTJ NVSRAMs,” <em>IEEE Transactions on Nanotechnology</em>, 2023.</p> <p>[5] P. Shukla, P. Kumar, and P. K. Misra, “An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder,” <em>IEEE Transactions on Circuits and Systems II: Express Briefs</em>, 2022.</p> <p>[6] S. Tripathi, S. Choudhary, and P. K. Misra, “A Novel STT-SOT MTJ Based Nonvolatile SRAM for Power Gating Applications,” <em>IEEE Transactions on Electron Devices</em>, 2022.</p> <p>[7] P. Shukla, P. Kumar, and P. K. Misra, “A Highly Reliable Dynamic Logic Based Hybrid MTJ/CMOS Magnetic Full Adder for High Performance and Low Power Application,” <em>IEEE Transactions on Magnetics</em>, 2022.</p> <p>[8] A. Verma, P. K. Yadav, M. Goswami, and P. K. Misra, “A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications,” <em>Wireless Personal Communications</em>, vol. 124, pp. 783–799, 2022.</p> <p>[9] Dipti, S. V. Singh, T. Kumawat, A. Bekal, P. K. Misra, and M. Goswami, “A 13.8 pJ/Conv-step Binary Search ADC with Reusable Comparator,” <em>AEU-International Journal of Electronics and Communications</em>, vol. 144, 2022.</p> <p>[10] P. K. Yadav, A. Verma, and P. K. Misra, “A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low Pass Filter for mmWave Band Applications,” <em>Journal of Circuits, Systems, and Computers</em>, June 2021.</p> <p>[11] P. K. Yadav and P. K. Misra, “Tunable Bandpass Filter using Double Resistive Feedback Floating Active Inductor for 5GHz Wireless LAN Applications,” <em>Analog Integrated Circuits and Signal Processing</em>, May 2021.</p> <p>[12] D. Sachan, M. Goswami, and P. K. Misra, “Design of Ultra-Low Power High-Q Single Ended Active Inductors for IF BPF of Receiver Frontend using 130nm BiCMOS Technology,” <em>Wireless Personal Communications</em>, April 2021.</p> <p>[13] A. Verma, P. K. Yadav, S. Ambulker, M. Goswami, and P. K. Misra, “A 36.7 mW, 28 GHz Receiver Frontend using 40nm RFCMOS Technology with Improved Figure of Merit,” <em>Analog Integrated Circuits and Signal Processing</em>, Jan. 2021.</p> <p>[14] J. K. Mishra, L. L. Mankali, K. Kandpal, P. K. Misra, and M. Goswami, “Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High Speed Applications,” <em>Journal of Circuits, Systems and Computers</em>, vol. 30, issue 15, 2021.</p> <p>[15] Dipti, S. V. Singh, R. Joshi, P. K. Misra, and M. Goswami, “A Reusable Stage Based Reduced Comparator Count Binary Search ADC,” <em>Analog Integrated Circuits and Signal Processing</em>, July 2020.</p> <p>[16] J. K. Mishra, B. B. Upadhyay, P. K. Misra, and M. Goswami, “Design and Analysis of SRAM Cell using Body Bias Controller for Low Power Applications,” <em>Circuits, Systems, and Signal Processing</em>, Nov. 2020.</p> <p>[17] J. K. Mishra, H. Srivastava, P. K. Misra, and M. Goswami, “Analytical Modelling and Design of 9T SRAM Cell with Leakage Control Technique,” <em>Analog Integrated Circuits and Signal Processing</em>, pp. 1–13, 2019.</p> <p>[18] D. Sachan, M. Goswami, and P. K. Misra, “A High-Q Floating Active Inductor using 130nm BiCMOS Technology and Its Application in IF Band Pass Filter,” <em>Analog Integrated Circuits and Signal Processing</em>, pp. 1–9, 2018.</p> <p>[19] D. Sachan, H. Kumar, M. Goswami, and P. K. Misra, “A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications using 180nm CMOS Technology,” <em>Wireless Personal Communications</em>, vol. 101, issue 1, pp. 391–403, 2018.</p> <p>[20] P. K. Misra and S. Qureshi, “A Technique to Improve the Performance of NPN HBT on Thin Film SOI,” <em>IEEE Journal of the Electron Devices Society</em>, vol. 1, no. 4, pp. 92–98, Apr. 2013.</p> <p style="text-align:justify"><strong><u>Conference Publications:</u></strong></p> <p>[1] A. Shrivastava, S. V. Nirmal, P. K. Misra, and P. K. Yadav, “A 2.4 GHz Down-Conversion Mixer with Improved Figure of Merit for WLAN Applications,” in <em>2025 IEEE 9th International Conference on Information and Communication Technology</em>, 2025.</p> <p>[2] R. S. Siddanath, A. Maurya, M. Gupta, P. K. Misra, M. Goswami, and K. Kandpal, “FinFET-Based Fast-Recovering Radiation-Hardened 14T (FRRH14T) SRAM for Space Applications,” in <em>2025 IEEE 22nd India Council International Conference (INDICON)</em>, pp. 1–6, 2025.</p> <p>[3] P. Chaurasia, A. Verma, M. Goswami, and P. K. Misra, “A Proposed Ultra Wide Band Low Noise Amplifier with Improved Gain Using Negative Impedance Circuit,” in <em>2025 IEEE 22nd India Council International Conference (INDICON)</em>, pp. 1–5, 2025.</p> <p>[4] S. Kannaujiya, P. Tiwari, K. Kandpal, and P. K. Misra, “Digitally Programmable FinFET/MTJ Voltage Controlled Oscillator for UWB Receiver,” in <em>2025 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)</em>, pp. 1–4, 2025.</p> <p>[5] S. Kourav, P. K. Yadav, M. Goswami, and P. K. Misra, “A Dual-Band Low-Noise Amplifier for 20 GHz 6G Communication and 77 GHz Radar Sensing,” in <em>2025 IEEE Microwaves, Antennas, and Propagation Conference (MAPCON)</em>, pp. 1–4, 2025.</p> <p>[6] P. K. Yadav, S. Ambulker, and P. K. Misra, “A FinFET-based Active Inductor for UWB Applications for 1.0–9.3 GHz Frequency,” in <em>2025 IEEE 7th International Conference on Emerging Electronics (ICEE)</em>, pp. 1–4, 2025.</p> <p>[7] R. Kanojia and P. K. Misra, “A 35 mW, 2.4 dB Noise Figure, 28 GHz Low-IF CMOS Receiver Front-end with 1 GHz Bandwidth,” in <em>2025 IEEE 7th International Conference on Emerging Electronics (ICEE)</em>, pp. 1–4, 2025.</p> <p>[8] P. Tiwari, A. Khatoon, and P. K. Misra, “An 18 nm FinFET with STT-PMA MTJs: A Hybrid Memory Cell Architecture for Energy-Efficient Analog In-Memory Computing,” in <em>2025 IEEE 7th International Conference on Emerging Electronics (ICEE)</em>, pp. 1–4, 2025.</p> <p>[9] P. Chaurasia, M. Goswami, and P. K. Misra, “An Ultra Low Power Variable Gain Amplifier Based on Negative Impedance for Low-IF Receiver Applications,” in <em>2025 IEEE 7th International Conference on Emerging Electronics (ICEE)</em>, pp. 1–4, 2025.</p> <p>[10] U. Singh, S. Kourav, R. Ahmad, K. Kandpal, and P. K. Misra, “A Proposed Dual-Band Low-Noise Amplifier With Tunable Gain and SNDR Characteristics,” in <em>2025 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)</em>, Bengaluru, India, 2025, pp. 1–5.</p> <p>[11] R. S. Siddanath, M. Gupta, R. D. Rao, S. K. Das, R. M. Hegde, P. K. Misra, M. Goswami, and K. Kandpal, “High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS Technology,” in <em>IEEE Computer Society Annual Symposium on VLSI (ISVLSI)</em>, 2025.</p> <p>[12] S. Kourav, M. Goswami, and P. K. Misra, “A 27 mW, 3 dB NF, 3 GHz Bandwidth CMOS Ultra Wideband Power Amplifier for Short Range Communication,” in <em>IEEE INDICON</em>, 2024.</p> <p>[13] S. Kannaujiya, K. Kandpal, and P. K. Misra, “A 16 mW 44 dB Gain Wideband Low Noise Amplifier for Ultra Wideband Applications,” in <em>IEEE INDICON</em>, 2024.</p> <p>[14] S. K. Jha, A. Khatoon, P. Tiwari, K. Kandpal, M. Goswami, and P. K. Misra, “Low IF CMOS Receiver with 3-stage LNA for Sub-GHz Communication,” in <em>International Symposium on Electronic System Design (ISES)</em>, 2024.</p> <p>[15] A. Khatoon and P. K. Misra, “A 72 mW, 50 MHz Bandwidth Low-IF CMOS Receiver Frontend with Improved Linearity and Dynamic Range,” in <em>International Symposium on Electronic System Design (ISES)</em>, 2024.</p> <p>[16] P. Tiwari and P. K. Misra, “Fast and Energy Efficient (0.01–2.78 aJ) Logic In Memory Module using SRAM Cells,” in <em>IEEE CONECCT</em>, 2024.</p> <p>[17] P. K. Yadav and P. K. Misra, “A Double-Resistive Feedback Active Inductor based Receiver Frontend using 40 nm CMOS Process for 28 GHz Applications,” in <em>IEEE INDICON</em>, 2022.</p> <p>[18] J. S. Kumar, B. Kumari, P. Kumar, A. Verma, P. K. Yadav, S. Ambulker, M. Goswami, and P. K. Misra, “Design of Transceiver at 865–867 MHz Band using UMC 180 nm Technology,” in <em>VDAT</em>, 2020.</p> <p>[19] J. K. Mishra, P. K. Misra, and M. Goswami, “Design of SRAM Cell using Voltage Lowering and Stacking Techniques for Low Power Applications,” in <em>IEEE Asia Pacific Conference on Circuits and Systems</em>, 2020.</p> <p>[20] J. K. Mishra, P. K. Misra, and M. Goswami, “A Low Power 7T SRAM Cell using Supply Feedback Technique at 28 nm CMOS Technology,” in <em>Seventh International Conference on Signal Processing and Integrated Networks</em>, 2020.</p> <p>[21] A. Verma, M. Goswami, and P. K. Misra, “Impact of Stages on the Performance of LNA Using RFCMOS and BiCMOS Technology for 5G Wireless Receiver Applications,” in <em>International Conference on Microelectronics, Circuits & Systems</em>, 2018.</p> <p>[22] D. Sachan, M. Goswami, and P. K. Misra, “A Comparative Study of 5G Wireless Receiver Frontend at 28 GHz Frequency using RFCMOS and BiCMOS Technologies,” in <em>International Conference on Microelectronics, Circuits & Systems</em>, 2018.</p> <p>[23] D. Sachan, M. Goswami, and P. K. Misra, “Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications,” in <em>IEEE International Conference on Consumer Electronics</em>, 2018.</p> <p>[24] A. Pandey, A. Verma, and P. K. Misra, “A 3.3 dB Noise Figure, 60 mW CMOS Receiver Front End for 865–867 MHz Band,” in <em>Conference on Information and Communication Technology (CICT)</em>, 2018.</p> <p>[25] P. Srivastava, P. K. Yadav, and P. K. Misra, “Design of 32-bit Asynchronous RISC CPU Using Micropipeline,” in <em>Conference on Information and Communication Technology (CICT)</em>, 2018.</p> <p>[26] R. Kumar, S. S. Yadav, A. K. Sihara, D. Sachan, and P. K. Misra, “Design of Active Inductor at 2.4 GHz Frequency using 180 nm CMOS Technology,” in <em>UPCON</em>, 2017, pp. 477–481.</p> <p>[27] P. K. Yadav and P. K. Misra, “Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180 nm CMOS Technology,” in <em>IEEE INDICON</em>, 2017.</p> <p>[28] P. K. Misra and S. Qureshi, “Analog/RF Performance of NPN SiGe HBT on Thin Film SOI Over −55 to +125 °C Temperature Range,” in <em>International Semiconductor Device Research Symposium</em>, Dec. 2013.</p> <p>[29] P. K. Misra and S. Qureshi, “Process and Device Simulations to Study the Impact of Ge Profile of 65 nm NPN SOI HBT with Buried Layer,” in <em>IEEE INDICON</em>, Dec. 2013.</p> <p>[30] P. K. Misra and S. Qureshi, “Speed Enhancement of NPN SiGe HBT on Thin Film SOI and Thin BOX Using Substrate Bias in (0V–3V) Range,” in <em>IEEE TENCON</em>, Indonesia, Nov. 2011, pp. 797–801.</p>