<p>Associate&nbsp;Professor</p>

<p style="text-align:justify">Department of Electronics and Communication Engineering, IIIT Allahabad</p>

<p><strong>Office:&nbsp;</strong>Room No.<strong>&nbsp;</strong>2224&nbsp;(CC-I), IIIT Allahabad</p>

<p><strong>Email:&nbsp;</strong>prasanna@iiita.ac.in</p>

<p><strong>Contact No:</strong>&nbsp;0532-2922111</p>

<p><strong><u>About Me:</u></strong></p>

<p style="text-align:justify">I obtained BTech (2005)&nbsp;and PhD (2014) from National Institute of Science and Technology, Berhampur and IIT Kanpur respectively. Since 2014, I am working as a faculty member in the department of Electronics and Communication Engineering at&nbsp;IIIT Allahabad. My specific area of interests are&nbsp;Analog/RF integrated circuit design, VLSI&nbsp;system design and Memory Design.&nbsp;I am&nbsp;associated with the VLSI Design/EDA laboratory at IIIT Allahabad. This laboratory has industry standard EDA tools (Cadence, Synopsys, Mentor Graphics, Xilinx, TCAD) and state-of-the-art technology design kits for designing integrated circuits and systems. The contributors of research work and publication details are given below.</p>

<p style="text-align:justify"><u><strong>PhD Students (Awarded):</strong></u></p>

<p style="text-align:justify">1. Dr. Divyesh Sachan,&nbsp;<span style="font-family:times new roman,times,serif; font-size:16px">Low Power RF Circuits</span></p>

<p style="text-align:justify">2. Dr. Jitendra Kumar Mishra,&nbsp;<span style="font-family:times new roman,times,serif; font-size:16px">Memory Design</span></p>

<p style="text-align:justify">3. Dr. Ankita Verma, CMOS Receiver</p>

<p style="text-align:justify">4. Dr. Pritesh Kumar Yadav, CMOS Receiver</p>

<p style="text-align:justify">5. Dr. Sandeep Tripathi,&nbsp;<span style="font-family:times new roman,times,serif; font-size:16px">Memory Design</span></p>

<p style="text-align:justify">6. Dr. Pratiksha Shukla,&nbsp;<span style="font-family:times new roman,times,serif; font-size:16px">Low Power Nonvolatile Circuits and Systems</span></p>

<p style="text-align:justify">7. Dr. Dipti (Analog to Digital Converter)</p>

<p style="text-align:justify"><u><strong>PhD Students (Ongoing):</strong></u></p>

<p style="text-align:justify">1. Mr. Anurag Pandey (High Speed Analog to Digital Converter)</p>

<p style="text-align:justify">2. Ms. Apsana Khatoon&nbsp; (Performance Study of CMOS Receiver)</p>

<p style="text-align:justify">3. Ms. Priyanka Tiwari (Non Volatile Circuits and Systems)</p>

<p style="text-align:justify">4. Mr. Sateesh Kourav&nbsp;(Ultra Wideband CMOS Transmitter)</p>

<p style="text-align:justify">5. Ms. Sandhya Kannaujiya&nbsp;(Ultra Wideband CMOS Receiver)</p>

<p style="text-align:justify">6. Mr. Ram Krishna Sharma&nbsp;(Ultra Wideband CMOS Transmitter)</p>

<p style="text-align:justify">7. Ms. Priyanka (Ultra Wideband CMOS Receiver)</p>

<p style="text-align:justify"><strong><u>Journal Publications:</u></strong></p>

<ol>
	<li style="text-align:justify">
	<p>Pritesh Kumar Yadav and Prasanna Kumar Misra, &quot;A 28-GHz mmWave Receiver Frontend With an Improved FOM of 15.56-dB for 5G New Radio in 130-nm BiCMOS Technology,&quot; in&nbsp;<em>IEEE Access</em>, 2026, Vol. 14, pp. 21200-21212.</p>
	</li>
	<li style="text-align:justify">
	<p><span style="font-family:helveticaneue regular,sans-serif; font-size:13.6px">A<span style="color:rgb(34, 34, 34); font-family:arial,sans-serif; font-size:13px">nurag Pandey, Kashi Bandla, Dipankar Pal, Dipti, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami, &quot;Performance improvement in asynchronous binary search ADC using bootstraaped sample and hold circuit and two stage ladder network&quot;,&nbsp;&nbsp;</span><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif; font-size:13px">Analog Integrated Circuits and Signal Processing, vol.124,J</span><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif; font-size:13px">uly 2025.</span></span></p>
	</li>
	<li style="text-align:justify">Sandeep&nbsp;Tripathi, Sudhanshu&nbsp;Choudhary and Prasanna Kumar Misra, &quot;An 8T PA Attack resilient NVSRAM for In-Memory-Computing Applications,&quot; IEEE Transactions on Circuits and Systems-I: Regular Papers,&nbsp;2023.</li>
	<li style="text-align:justify">Sandeep&nbsp;Tripathi, Sudhanshu&nbsp;Choudhary and Prasanna Kumar Misra, &ldquo;Highly Reliable, Stable and Store Energy efficient 8T/9T-2D-2MTJ NVSRAMs&rdquo; IEEE Transactions on Nanotechnology, 2023.</li>
	<li style="text-align:justify">Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra, &quot;An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder&quot;&nbsp;&nbsp;IEEE Transactions on Circuits and Systems II: Express Briefs, 2022.</li>
	<li style="text-align:justify">Sandeep Tripathi, Sudhanshu Choudhary, Prasanna Kumar Misra, &quot; A Novel STT-SOT MTJ Based Nonvolatile SRAM for power gating applications,&quot; IEEE Transactions on Electron Devices 2022.</li>
	<li style="text-align:justify">Pratiksha Shukla, Pramod Kumar, Prasanna Kumar Misra, &quot; A Highly Reliable Dynamic Logic Based Hybrid MTJ/CMOS Magnetic Full adder for High Performance and Low Power Application,&quot; IEEE Transactions on Magnetics, 2022.</li>
	<li style="text-align:justify">Ankita Verma, Pritesh Kumar Yadav, Manish Goswami and Prasanna Kumar Misra,&nbsp;&ldquo;A Differential LNA Architecture with Improved Figure of Merit Using 40&nbsp;nm UMC CMOS Technology for mmWave Band Receiver Applications, Wireless Personal Communications, Vol. 124,&nbsp;pages783&ndash;799,&nbsp; 2022.</li>
	<li style="text-align:justify">Dipti, Sajai Vir Singh, Tushar Kumawat, Anush Bekal, Prasanna Kumar Misra, Manish Goswami, &quot; A 13.8 pJ/Conv-step binary search ADC with reusable comparator&quot;&nbsp;AEU-International Journal of Electronics and Communications,&nbsp;Vol. 144, 2022.</li>
	<li style="text-align:justify">Pritesh Kumar Yadav, Ankita Verma, Prasanna Kumar Misra, &ldquo;A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low Pass Filter for mmwave Band Applications,&rdquo; Journal of Circuits, Systems, and Computers, June 2021.</li>
	<li style="text-align:justify">Pritesh Kumar Yadav, Prasanna Kumar Misra, &ldquo;Tunable Bandpass filter using double resistive feedback floating active inductor for 5GHz Wireless LAN Applications,&rdquo; Analog Integrated Circuits and Signal Processing, May 2021.</li>
	<li style="text-align:justify">Divyesh Sachan, Manish Goswami and Prasanna Kumar Misra, &ldquo;Design of ultra-low power high-Q single ended Active Inductors for IF BPF of Receiver Frontend using 130nm BiCMOS Technology,&rdquo; Wireless Personal Communications, April 2021.</li>
	<li style="text-align:justify">Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami and Prasanna Kumar Misra, &ldquo;A 36.7 mW, 28 GHz receiver frontend using 40nm RFCMOS technology with improved Figure of Merit,&rdquo; Analog Integrated Circuits and Signal Processing , Jan 2021.</li>
	<li style="text-align:justify">Jitendra Kumar Mishra, Lakshmi Likhitha Mankali, Kavindra Kandpal, Prasanna Kumar Misra, Manish Goswami, &quot; Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High Speed Applications&quot;&nbsp;Journal of Circuits, Systems and Computers, Vol. 30, ISsue 15, 2021.</li>
	<li style="text-align:justify">Dipti,&nbsp;Sajai Vir Singh,&nbsp;Rohit Joshi,&nbsp;Prasanna Kumar Misra&nbsp;&amp;&nbsp;Manish Goswami, &ldquo;A reusable stage based reduced comparator count binary search ADC,&rdquo; Analog Integrated Circuits and Signal Processing , July 2020.</li>
	<li style="text-align:justify">Jitendra Kumar Mishra, Bharat Bhushan Upadhyay, Prasanna Kumar Misra, Manish Goswami, &quot; Design and Analysis of SRAM Cell using Body Bias Controller for Low Power Applications,&quot;&nbsp;&nbsp;Circuits, Systems, and Signal Processing, November 2020.</li>
	<li style="text-align:justify">Jitendra Kumar Mishra, Harshit Srivastava, Prasanna Kumar Misra and Manish Goswami, &ldquo;Analytical modelling and design of 9T SRAM cell with leakage control technique,&rdquo; Analog Integrated Circuits and Signal Processing 2019, pp. 1-13.</li>
	<li style="text-align:justify">Divyesh Sachan, Manish Goswami and Prasanna Kumar Misra, &ldquo;A High-Q Floating Active Inductor using 130nm BiCMOS Technology and Its Application in IF Band Pass Filter,&rdquo; Analog Integrated Circuits and Signal Processing 2018, pp. 1-9.</li>
	<li style="text-align:justify">Divyesh Sachan, Harshbardhan Kumar, Manish Goswami and Prasanna Kumar Misra, &ldquo;A 2.4 GHz low power low phase-noise enhanced FOM VCO for RF Applications using 180nm CMOS Technology,&rdquo; Wireless Personal Communications 2018, Volume 101, Issue 1,&nbsp;pp 391&ndash;403.</li>
	<li style="text-align:justify">Prasanna Kumar Misra and S. Qureshi, &ldquo;A Technique to Improve the Performance of NPN HBT on thin film SOI,&rdquo; IEEE Journal of the Electron Devices Society, Vol. 1, No. 4, April 2013, pp. 92-98.</li>
</ol>

<p style="text-align:justify"><strong><u>Conference Publications:</u></strong></p>

<ol>
	<li style="text-align:justify">
	<p>U. Singh, S. Kourav, R. Ahmad, K. Kandpal and Prasanna Kumar Misra, &quot;A Proposed Dual-Band Low-Noise Amplifier With Tunable Gain and SNDR Characteristics,&quot;&nbsp;<em>2025 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)</em>, Bengaluru, India, 2025, pp. 1-5.</p>
	</li>
	<li style="text-align:justify">
	<p><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif">Ravi S Siddanath, Mohit Gupta, R Dhirendra Rao, Souvik Kumar Das, Raghavendra Manjunath Hegde, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal, &quot;High-Precision BGR Design with Advanced Curvature Compensation &amp; Optimized Layout in 28 nm CMOS Technology&quot;&nbsp;IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2025.&nbsp;&nbsp;</span></p>
	</li>
	<li style="text-align:justify">
	<p><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif">Sateesh Kourav, Manish Goswami, Prasanna Kumar Misra, &quot;A 27 mW, 3 dB NF, 3 GHz Bandwidth CMOS Ultra Wideband Power Amplifier for Short range Communication&quot;, INDICN 2024.&nbsp;</span></p>
	</li>
	<li style="text-align:justify">
	<p><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif">Sandhya Kannaujiya, Kavindra Kandpal, Prasanna Kumar Misra, &quot; A 16 mW 44 dB Gain Wideband Low Noise Amplifier for Ultra Wideband Applications&quot; INDICON 2024.&nbsp;</span></p>
	</li>
	<li style="text-align:justify">
	<p><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif">Shivam Kumar Jha, Apsana Khatoon, Priyanka Tiwari, Kavindra Kandpal, Manish Goswami, Prasanna Kumar Misra, &quot;Low IF CMOS Receiver with 3-stage LNA for Sub-GHz Communication&quot; ISES 2024.</span></p>
	</li>
	<li style="text-align:justify">
	<p><span style="color:rgb(34, 34, 34); font-family:arial,sans-serif">Apsana Khatoon, Prasanna Kumar Misra, &quot;A 72 mW, 50 MHz Bandwidth Low-IF CMOS Receiver Frontend with improved Linearity and Dynamic Range&quot;, ISES 2024.&nbsp;</span></p>
	</li>
	<li style="text-align:justify">
	<p>Priyanka Tiwari and Prasanna Kumar Misra, &quot;Fast and Energy Efficient (0.01-2.78 aJ) Logic In Memory Module using SRAM Cells,&quot; IEEE CONECCT 2024.</p>
	</li>
	<li style="text-align:justify">
	<p>Pritesh Kumar Yadav and Prasanna Kumar Misra, &quot; A Double-Resistive Feedback Active Inductor based Receiver Frontend using 40 nm CMOS Process for 28 GHz Applications&quot;, IEEE INDICON 2022.</p>
	</li>
	<li style="text-align:justify">Jai Shankar Kumar, Babli Kumari, Prashant Kumar, Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami, Prasanna Kumar Misra, &quot; Design of Transceiver at 865-867 MHz Band using UMC 180 nm Technology,&rdquo; VDAT 2020.</li>
	<li style="text-align:justify">Jitendra Kumar Mishra, Prasanna Kumar Misra, Manish Goswami, &quot; Design of SRAM Cell using Voltage Lowering and Stacking Techniques for Low Power Applications,&quot; IEEE Asia Pacific Conference on Circuits and Systems&nbsp;2020.</li>
	<li style="text-align:justify">Jitendra Kumar Mishra, Prasanna Kumar Misra, Manish Goswami, &quot; A Low Power 7T SRAM Cell using Supply Feedback Technique at 28 nm CMOS Technology,&quot; Seventh International Conference on Signal Processing and Integrated Networks&nbsp; 2020.</li>
	<li style="text-align:justify">Ankita Verma, Manish Goswami and Prasanna Kumar Misra, &ldquo;Impact of Stages on the Performance of LNA Using RFCMOS and BiCMOS Technology for 5G Wireless Receiver Applications,&rdquo; International Conference on Microelectronics, Circuits &amp; Systems,&nbsp; 2018.</li>
	<li style="text-align:justify">Divyesh Sachan, Manish Goswami and Prasanna Kumar Misra, &ldquo;A Comparative Study of 5G Wireless Receiver Frontend at 28GHz Frequency using RFCMOS and BiCMOS Technologies,&rdquo; International Conference on Microelectronics, Circuits &amp; Systems,&nbsp; 2018.</li>
	<li style="text-align:justify">Divyesh Sachan, Manish Goswami and Prasanna Kumar Misra, &ldquo;Analysis of Modulation Schemes for Bluetooth-LE Module for Internet-of-Things (IoT) Applications,&rdquo; IEEE International Conference on Consumer Electronics, 2018.</li>
	<li style="text-align:justify">Awdhesh Pandey, Ankita Verma, Prasanna Kumar Misra, &quot; A 3.3 dB Noise Figure, 60 mW CMOS Receiver Front End for 865-867 MHz Band&quot;, Conference on Information and Communication Technology (CICT), 2018.</li>
	<li style="text-align:justify">Pranjal Srivastava,&nbsp;Pritesh Kumar Yadav, Prasanna Kumar Misra, &ldquo;Design of 32 bit&nbsp; Asynchrnous RISC CPU Using Micropipeline&rdquo;, Conference on Information and Communication Technology (CICT) 2018.</li>
	<li style="text-align:justify">Rajan Kumar, Sonu Singh Yadav, Ankit Kumar Sihara, Divyesh Sachan and Prasanna Kumar Misra, &ldquo;Design of Active Inductor at 2.4 GHz frequency using 180 nm CMOS Technology&rdquo;, UPCON 2017, pp.477-481.</li>
	<li style="text-align:justify">Pritesh Kumar Yadav and Prasanna Kumar Misra, &ldquo;Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180nm CMOS Technology&rdquo; INDICON 2017.</li>
	<li style="text-align:justify">Prasanna Kumar Misra and S. Qureshi, &ldquo;Analog/RF Performance of NPN SiGe HBT on Thin Film SOI Over -55 to&nbsp; +125 degC Temperature&nbsp; Range.&rdquo; International Semiconductor Device Research Symposium, December 2013.</li>
	<li style="text-align:justify">Prasanna Kumar Misra and S. Qureshi, &ldquo;Process and Device Simulations to Study The Impact of Ge Profile of 65 nm NPN SOI HBT with Buried Layer,&rdquo; IEEE INDICON, December 2013.</li>
	<li style="text-align:justify">Prasanna Kumar Misra and S. Qureshi, &ldquo;Speed Enhancement Of npn SiGe HBT On Thin Film SOI and Thin BOX Using Substrate Bias in (0V-3V) Range,&rdquo; IEEE TENCON, November 2011, Indonesia, pp. 797-801.</li>
</ol>