Your IP : 216.73.216.40
<html><head>
<meta http-equiv="content-type" content="text/html; charset=UTF-8">
<title>Dr. Bibhas Ghoshal</title>
<style type="text/css">
body {margin:20px}
a {text-decoration:none}
a:hover {text-decoration:none; background:#0088aa; color:#eeeeff}
table {border:none}
td {border:none}
th {border:none}
#withbd {border:none; background:#ddddaa}
#withbd:hover {background:#ddddaa}
body {
background-color:#eeeeff;
}
p {text-align: justify}
li {text-align: justify}
</style>
</head><body alink="#000000" bgcolor="#eeeeff" link="#0088aa" text="#000000" vlink="#0088aa">
<font face="Helvetica">
<h2 align="center">Publications of Dr. Bibhas Ghoshal </h2>
<h3 align="left">Journal Papers</h3>
<ol>
<li><b>Bibhas Ghoshal</b>; Kanchan Manna; Sanatanu Chattopadhyay; Indranil Sengupta, <i> "In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers," </i> IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.PP, no.99, pp.1,1,
doi: 10.1109/TVLSI.2015.2393714<br>[<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7069199">Download</a>]
<h3 align="left">Conference Papers</h3>
<ol>
<li><b>Bibhas Ghoshal</b>; Chittaranjan Mandal; Indranil Sengupta,<i> "Re-using Refresh for Self-Testing DRAMs," </i>Proceedings of the International Symposium on Electronic System Design (ISED), NTU Singapore, pp. 118-122, 10-12 December 2013,
doi: 10.1109/ISED.2013.30<br>[<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6808653">Download</a>]
</li><li><b>Bibhas Ghoshal</b>; Indranil Sengupta, <i> "A Distributed BIST Scheme for NoC-Based Memory Cores," </i> Proceedings of the Euromicro Conference on Digital System Design (DSD), Santander, Spain, pp. 567-574, 4-6 September 2013,
doi: 10.1109/DSD.2013.67<br>[<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6628328">Download</a>]
</li><li><b>Bibhas Ghoshal</b>, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay, <i>
"Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip", </i> Proceedings of the 16th International Symposium on Progress in VLSI Design and Test (VDAT), Shibpur, India, pp. 343-349, 1-4 July, 2012,<br>[<a href="http://dx.doi.org/10.1007/978-3-642-31494-0_39">Download</a>]
<h3 align="left">Theses</h3>
<ul>
<li><b>PhD Thesis:</b> <i>Improved Test Techniques For
Network-on-Chip Based Memory Systems</i>, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Jan 2015.<br>[<a href="thesis.pdf">Download</a>]
</li></ul>
</font>
</body></html>