Welcome to the NANOSCALE ELECTRO-THERMAL LABORATORY (NET LAB) group at Indian Institute of Information Technology-Allahabad

The backbone of any semiconductor foundry is driven by the much celebrated silicon based field effect transistors (FETs), that shrinks with each technology node generation. This downscaling however has a lower limit beyond which the active material-Si, rapidly changes its electronic (for example increased band gap, increased transport effective masses, etc.) as well as thermal properties (for example a decreased thermal conductivity, etc.).

Not only this, on the device level the controlling element- gate, starts loosing control over its active region (which is the Si-channel), thereby enhancing several leakage currents and degrading the overall transistor perfromance. A possible solution to the later is achieved by completely modifying the transistor geometry, doping profiles, implanting strain, etc., the result of which has boosted the era of so called non-planer/multi-gate or elevated Si FETs, strained FETs, tunnnel FETs, etc. The solution to the former one is equally challenging- i.e., to replace the base material –silicon with a new one such that it should also be compatible to the existing process technology. This has thus set the roadmap of searching for novel materials, and the FETs based on these are thus called as post-Silicon FETs or devices. This era is also usually called as "More than Moore".  As dictated by the INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS-2013 (ITRS) industry standard,

"...This is accomplished by addressing two technology-defining domains: 1) extending the functionality of the CMOS platform via heterogeneous integration of new technologies, and 2) stimulating invention of a new information processing paradigm. The relationship between these domains is schematically illustrated in Figure ERD1. The expansion of the CMOS platform by conventional dimensional and functional scaling is often called “More Moore”. The CMOS platform can be further extended by the “More-than-Moore” approach which was first introduced into ERD chapter in 2011. On the other hand, new information processing devices and architectures are often called “Beyond CMOS” technologies and have been the main subjects of this chapter. The heterogeneous integration of “Beyond CMOS”, as well as “More-than-Moore”, into “More Moore” will extend the CMOS platform functionality to form ultimate “Extended CMOS...”.


Figure ERD1: Relationship among More Moore, More-than-  Moore, and Beyond CMOS (Courtesy of Japan ERD) (Adapted from ITRS-2013 ERD Section). Figure 2. FET transfer characteristics showing ID (on a logarithmic scale on the left and a linear scale on the right) versus the gate–source voltage, VGS. The transistor is considered to be switched on when VGS is equal to the maximum voltage supplied to the device, VDD. The higher the slope in the subthreshold region (VGS < Vth), the better the transistor switch-on characteristics become. Above threshold, the change in ID for a given change in VGS is called the terminal transconductance, gmt. (Nature Nanotech., vol. 5, pp. 487, (2010)).

The Nanoscale ELectro-thermal laboratory or the NET lab was started in 2014 by Dr. Sitangshu Bhattacharya and focuses strongly on electrical and thermal management of emerging materials and devices, both in bulk as well as in the submicron or nanoscale order. At present we are mainly engaged to conduct theoretical research to explain electronic and phononic transport properties like electrical and thermal conductivity, Seebeck coefficient, interface physics, noise and RF modelling in 2D graphene/dichalcogenides based heterostructure transistors, Joule-heating effect in interconnects and vias and RF/Analog ICs and low power VLSI systems. We use the Boltzmann transport theory and many body physics based advanced analytical formalisms with mathematical and computational tools like Green's function, first principle techniques, etc. to explain the said properties. The experimental facilities are described in the "facility" section.

The lab is currently funded by the Department of Science and Technology (DST), India and IIIT-Allahabad.

In case, if you are interested to join us as a post-doc/PhD/M.Tech, you may directly write us along with a one page write up specifying your research interest. You may also want to look in the "Reseach Areas" and "Opportunity" section in the top of this page for extensive discussions.


1st June, 2016: Miss Himani Mishra Joined our Lab as a Int. PhD student. Details ...

3rd May, 2016: Dr. Rekha Verma was elected as Vice-Chair of IEEE-EDS Uttar Pradesh Section. Details ...

14th January 2016: JRF Opening: There is an opening of a JRF position in NET LAB for the project related to graphene transistors. Details ...

Faculties involved

Sitangshu Bhattacharya
Assistant Professor, Ph.D: Jadavpur University, 2009, India.

Rekha Verma
Assistant Professor, Ph.D: IISc Bangalore, 2013, India.

Research interests:
Computational Nanoelectronics:
Many-Body Perturbation Formulations of Electrical & Phonon Transport in 2D materials, Physics of Excitons and Surface Passivations, Thermoelectricity, Self-Heating in Interconnects