Dr. Manish Goswami holds the position of an Associate Professor at Indian Institute of Information Technology (IIIT-A). He joined IIIT-A in the year 2008 in the Microelectronics Division. He has taught several courses at the Bachelors and the Master levels at IIIT-A. As an academician he puts in 16+ fruitful years in the field of teaching and research. Prior to his expertise here at IIIT-A he served as a faculty in many other universities. He is the member of IEEE and VLSI Society of India.
To add to his merits he currently holds the position of Head of the Department (ECE), in addition to it he is serving as Chief Proctor at the Indian Institute of Information Technology, Allahabad.
Besides research and academics, his present work also involves setting up and establishing a collaboration for the chip fabrication work at IIIT-A.
Recently Dr. Goswami and his team has designed, fabricated and successfully tested variable resolution ADC chip.
His research interest includes Analog and Mixed Signal VLSI design Circuits, Low Power VLSI Circuit Design, Data Converters, Noise Modeling and Digital Design etc.
He’s also guiding students for Ph.D and M.Tech thesis.
Apart from academics Dr. Goswami loves playing badminton, chess, carom and has been actively participating in the overall developmental activities of the institute.

Work Experience

Working in Indian Institute of Information Technology Allahabad (IIIT-A) – a Govt. of India organization established as Center of Excellence in Information Technology and Allied Areas since June 2008-till date

  • Started my career in IIITA as Lecturer and then promoted to Assistant Professor Electronics and Communication Deptt.
    • Work includes research and teaching M.Tech and B.Tech students
    • Establishment of Laboratories
    • Training the students and guiding MTech Thesis & Ph.D scholars
    • Contribution in M.Tech and B.Tech Curricula
    • Establishing Chip-fabrication (Foundry Support) facility and handling of microelectronics softwares
    • Microelectronics Stream coordinator
    • Contributing in other extra-curricular activities of the institute etc.
  • July 2005- May 2008
    Worked as Lecturer in Birla Institute of Technology (B.I.T) Mesra, Ranchi.
    • Work includes research and teaching M.Tech and B.Tech students
    • Established Laboratories and Guided MTech and BTech Thesis
    • Developed courses for M.Tech and B.Tech streams
    • Handled Registration activities, Website extra-curricular activities etc.
  • July 2002-June 2005
    Worked as Lecturer and Incharge–ECE deptt. in Jaipur Engineering College and Research Centre (J.E.C.R.C) Jaipur.
    • Handling the departmental activities, Teaching B.Tech students, Exam Incharge, Team member of planning and Improvement Cell etc.
  • Feb 1999-May 2000
    Worked as Assistant Engineer in EPABX Company Mumbai.
    • Work includes handling EPABX Cards, Later promoted to become Team member of R/D software.

Administrative Experience

  • Worked as Coordinator, Electronics and Communication Deptt IIITA
  • Worked as Incharge Exam & Admission Cell in I.I.I.T-A
  • Worked as Warden Boys Hostel,I.I.I.T-A.
  • Worked as Incharge, Electronics and Communication Deptt, JECRC Jaipur

Academic Achievements

  • 2 Ph.D awarded under my supervision
  • 3 Ph.D currently enrolled under my supervision
  • Guided more than 20 MTECH thesis and few currently undergoing.

Research Interest

  • Analog and Mixed Signal VLSI design Circuits
  • Low Power Circuit Design
  • Data Converters
  • Memory Design


  • Doctor of Philosophy (Ph.D), Submitted 2010 Awarded 2012 Specialization: VLSI Design
    B.I.T Mesra, Ranchi, India
    Topic: Offset and noise cancellation suitable for biomedical and other low frequency signal recording.
  • Masters of Engineering (M.E), 2002
    M.N.I.T Jaipur, Rajasthan with First Class.
  • Bachelors of Engineering (B.E), 1998
    Mumbai University with First Class.

Technical Skills

  • Hardware description Language VHDL, Verilog
  • Programming Language C, C++, MATLAB
  • Simulation and Layout Tool Cadence, Tanner, Model Sim, MATLAB, Xilinx, Active HDL, Synplify Pro, etc.


ASIC Implementation of low power variable resolution ADC

High resolution ADC dissipates high power and occupies large silicon area. A solution to save power in ADC is therefore to detect the current operating condition and vary the resolution accordingly.

In this ADC design, resolution is dynamically adjusted according to the given channel conditions. The approach followed in saving power is done by switching some of the stages of the ADC to the standby mode (depending upon the input strength) where power dissipation is only due to the leakage current.

The variable resolution ADC has been designed using Tanner tool on 500nm CMOS technology (AMIS_0.5_CFN kit) and chip is fabricated from MOSIS foundry.

This is the first chip fabrication done by my group in IIITA .

An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC

Comparators are considered to be one of the rudimentary building blocks in most ADCs. Major criterion for an ADC design is high speed, low power and lesser real estate over the chip. In the conventional dynamic latched comparators a small input-voltage difference at the input terminals is pulled up to a full scale digital level in a short span of time, by a positive feedback mechanism (regenerative latch). Due to the random offset errors and internal parasitic/external load capacitances mismatches they suffer a lot of accuracy issues. To overcome this inaccuracy issue, the conventional architecture used a separate preamplifier stage anteceding the positive feedback stage due to which it could amplify a small difference in the input voltage to a full scale digital output, negating the kickback noise. But for an ADC with a feature of high speed and low power application, a comparator without the preamplifier is preferred since it suffers from high static power dissipation. The present work deals with increasing the speed of conversion for an 8-bit ASAR ADC which is done by incubating a modified dynamic latch based comparator as proposed. In the reset phase the output nodes has to be charged up to the initial supply voltage level. This charging of the output nodes induces latency in the process of comparison. We propose a modified approach to tackle this dead time required to reset and improve the speed of comparison. This will in turn make the ASAR ADC to fasten the process of conversion.

Awards & Honours

  1. The team under my supervision has won All India Mentor Graphics University Design contest 2014 –prize won 1.5 L
  2. PI of SMDPC2SD project of Govt of India
  3. Co-PI in DST awarded sponsored project on Solar Cell The team under my supervision Runners Up in Cadence All India Design contest 2013–prize won .5 L
  4. Top 5 Finalist in Cadence All India Design contest 2012
  5. Went to EPFL Switzerland for 1 month under the Indo Swiss Joint Research Programme (ISJRP) in the project "Micro and Nanoelectronic Devices and Technologies for Environment Monitoring".
  6. Presented a expert talk on –VLSI design during the national workshop on “Electronics System Design and Manufacturing” held on July 18, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi
  7. Presented a expert lecture during the workshop on- Advanced VLSI Design Automation at Sam Higginbottom Institute of Agriculture, Technolgy & Sciences (Allahabad Agriculture University) - held on 8th Sept 2012.
  8. Presented a expert talk on –Crosstalk and noise in digital Systems during the national workshop on “Timing Analysis of Digital VLSI Circuits” held on Nov 3-4, 2012 at IIIT-A sponsored by Deptt of IT, MCIT GOI New Delhi.
  9. Best Research Paper Award in IEEE Int. Conf. on Emerging Trends in Elect. Comp. Tech., India.
  10. Throughout topper at B.E level and GATE Qualified.
  11. Established collaboration for the chip fabrication work in IIIT-A.


  1. Anush Bekal, Saloni Varshney, Kamal Prakash Pandey and Manish Goswami, "Linear relationship ADC with complimentary switch-based bootstrapped sample and hold circuit", International Journal of Electronics, ol.104, Issue. 9, pp.1227-1246, 2017.
  2. Anush Bekal, Shabi Tabassum and Manish Goswami, "Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC", Journal of Circuits, Systems, and Computers, vol. 26, Issue 05, May 2017.
  3. Divyesh Sachan, Harish Peta, Kamaldeep Singh Malik and Manish Goswami, “Low power Multi-threshold 7T SRAM Cell", 59th IEEE Midwest Symp. Circ. Systems (MWSCAS), Oct 16-19, Abu Dhabi, UAE, 2016.
  4. Apoorva Pathak, Divyesh Sachan, Harish Peta and Manish Goswami, “A Modified SRAM BASED Low Power Memory Design”, 29th IEEE VLSI Design Conf. (VLSID), Jan 2-4, Kolkata , India 2016.
  5. Anush, Rohit Joshi, Manish Goswami. B. R. Singh and A Srivastava, “An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC”, IEEE ISVLSI, France 2015.
  6. P. Joshi, Manish Goswami and D Pal, “Design of Quadrature Amplitude Modulation based DC offset cancellation circuit,” Int. J. Electronics Letters, March 2015.
  7. Anush, Manish Goswami. B. R. Singh and D. Pal, “A low power 8-bit Asynchronous SAR ADC design using Charge Scaling DAC ” IEEE ISED, 2014.
  8. Saloni, M. Goswami, B R Singh, Ashok Srivastava “Low Power Variable Resolution ADC ” J. of Low Power Electronics Vol 2, No 10, pp. 236-246, 2014.
  9. Ashwath Rao, Anshuman Dwivedi, Manish Goswami, B. R. Singh, “Effect of nitrogen containing plasma on interface properties of sputtered ZrO2 thin films on silicon”, Elsevier Materials Sciences in Semiconductor Processing, Vol 19, pp 145-149, 2014.
  10. Shabi, Anush, and Manish Goswami., “A Low Power Preamplifier Latch based Comparator Using 180nm CMOS Technology” accepted in IEEE Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia) -2013.
  11. Jitendra Jain, Shobhit Singh and Manish Goswami, “Design of Wideband Current Conveyor (CC-II) based Oscillator for Low-Voltage Application using 180nm CMOS Technology,” accepted in CARE-2013.
  12. Saloni, Manish Goswami, B R Singh, “4-6 Variable resolution ADC ” accepted in IEEE- ISED -2013 held in NTU Singapore from 12-14 Dec, 2013.
  13. Atul Kumar, Ashwath Rao, Manish Goswami, B. R. Singh, “Electrical Characterization of MfeOS gate stacks for ferrielectric FETs”, Elsevier Materials Sciences in Semiconductor Processings, Vol 16, pp 1603-1607, 2013.
  14. M. Goswami, D. Verma, Saloni and B R Singh, “Reduced Comparator High Speed Low Power Flash ADC using 90nm CMOS Technology”, Springer’s Analog Integrated circuits and Signal Processing, Vol 74, No 1, pp. 267-278, 2013.
  15. Kavindra Kandpal, Saloni Varshney, and Manish Goswami, “A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs,” Journal of Automation and Control Engineering in Vol. 1 No. 3, 2013.
  16. Manish Goswami et al., “High Performance Hardware Implementation of AES using Minimal Resources” accepted in IEEE- ISSP 2013.
  17. Saloni, Manish Goswami, B R Singh, “Comparator-Multiplexer Based 6 bit 1.4GS/s Low Power ADC” accepted in IEEE- DTIS (Design and Technology of Integrated Systems in Nanoscale Era )-2013 held in UAE from 26-28 March 134-139, 2013.
  18. Saloni, Manish Goswami, B R Singh, “A 5-bit 1.5 GS/s ADC Using Reduced Comparator Architecture” accepted in IEEE- IDT (International Design and Test Symposium)-2012 held in Doha.
  19. Hari Kakara, Manish Goswami, and B.R.Singh “Design and Simulation of low-g single axis SOI MEMS Capacitive Accelerometer”, Int. J. Contemporary Research in Engg. Tech, Vol. 2, No 1, pp. 63-69, 2012.
  20. R. Kumari, Manish Goswami, B.R.Singh “The Impact of Channel Engineering on Short Channel Behavior of Nano Fin-FETs”, Int. J. Nanoscience, No 2, pp. 21-26, March, 2012.
  21. Manish Goswami, Manoj Malik, and D Pal, “A Single Channel QAM Based DC Offset Cancellation Circuit for High Gain Instrumentation Amplifier System,” in Proc. Int. Conf. Information, Communication Embedded Systems., vol. 1, Chennai, India, 2012.
  22. Manish Goswami, Prateesh Shukla, Piyush Joshi, Manoj Malik, and D Pal, “A Low Input Referred Noise Amplifier System for Biomedical Application,” in Proc. IEEE Int. Conf. Electronics Computer Technology., vol. 1, Kanyakumari, India, 2012, pp. 430-434. ACCEPTED FOR PUBLICATION IN Journal of Industrial and Intelligent Information.
  23. Akanksha Bansal, Manish Goswami, and B R Singh, “Optimization of Short Channel Effects in sub 40nm Bulk MOSFET Using Halo Doping,” in Proc. IEEE Stu. Conf. Engineering Systems., vol. 1, Allahabad, India, 2012.
  24. Manish Goswami, and Smriti Khanna, “DC Suppressed High Gain Active CMOS Instrumentation Amplifier for Biomedical Application,” in Proc. IEEE Int. Conf. Emerging Trends Elect. Comp. Tech., vol. 1, Nagercoil, India, 2011, pp. 747-751.
  25. Manish Goswami, and Sudhanshu kannoujiya, “High Performance FPGA Implementation of AES Algorithm with 128-Bit Keys,” in Proc. IEEE Int. Conf. Advances Computing Comm., vol. 1, Himarpur, India, 2011, pp. 281-286.
  26. M. Goswami, A. Saha, M. Chandra and D. Pal, “Novel high Speed MCML 8 bit by 8 bit Multiplier,” in Proc. IEEE Int. Conf. Devices and Communication in Eng. Tech., vol. 1, Ranchi, India, 2011, pp. 978-982.
  27. D. Pal, and M. Goswami, “A Clocked High Pass Filter Based Offset Cancellation Technique for High Gain Biomedical Amplifiers,” Int. J. Electronics-Taylor Francis., vol. 97, no. 5, pp. 539- 552, May 2010.
  28. D. Pal, A. Srinivasulu, and M. Goswami, “Novel Current Mode Waveform Generator with independent frequency and Amplitude Control,” in Proc. IEEE Int. Symp. Circuits Systems (ISCAS)., Taipei, Taiwan, 2009, pp. 2946-2949.
  29. R. Sebastian, M. Malik, M. Goswami, and D. Pal, “VLSI Implementation of Controller Architecture Unit of Digital Thermometer Recording System,” in Proc. National Seminar on Devices, Circuits and Comm., vol. 1, Ranchi, India, 2008.
  30. D. Pal, M. Goswami, and G Krishan, “Novel Approach of High Speed Multipliers,” in Proc. IEEE Int. Conf. Recent App. Soft Computing in Eng. Tech., vol. 1, Alwar, India, 2007, pp. 349-352.
  31. G. Krishan, M. Goswami, and N. Khurana, “Design of High Speed Multiplier,” in Proc. National Conference on High Performance Computing for Next Generation., vol. 1, Tangori, Punjab, India, 2007.

Ph.D. Students

  • Saloni Varshney

    email: varshney.shaloni@gmail.com
    Ph.D. Thesis: ASIC Implementation of low power, variable resolution ADC.
    Research Interest:VLSI Design, Low Power ADC converter.

  • Anush Bekal

    email: anush.bekal.in@ieee.org
    Ph.D. Thesis: Low power design of an 8-bit asynchronous SAR ADC using 180nm CMOS technology
    Tools and Software Using: Cadence Virtuoso, H-Spice, LT Spice, Mentor Graphics Design Compiler Tanner EDA, VCS,.
    Research Interest: Analog IC Design, Analog VLSI Design, Mixed Signal Design, Digital Design, VLSI Circuits

  • Joyline Germine D'SA

    email: dsa.joyline@gmail.com
    Ph.D. Thesis: Simulation, fabrication and characterization of drug delivery systems using polymers
    Tools and Software Using:Cadence, Keithely SCS-4200,Silvaco, Tanner, Xilinx
    Research Interest: VLSI Technology

  • email:
    Ph.D. Thesis: RF
    Tools and Software Using: Cadence Virtuoso, PSpice, Tanner, Xilinx
    Research Interest: Analog and Mixed Signal VLSI Design, RF Design

  • Jitendra Mishra

    email: rse2016506@iiita.ac.in
    Ph.D. Thesis: Enhanced Performance of SRAM using various circuit technique.
    Tools and Software Using:Cadence Virtuoso, Tanner, Xilinx
    Research Interest: Mixed Signal Design, Memory Design, Low power design.


E/8, IIIT Jhalwa

Allahabad (U.P)

India, Pin-211012

Email: manishgoswami@iiita.ac.in